diff -Naur u-boot-2011.06/arch/arm/cpu/cortex-m3/config.mk u-boot-2011.06-lpc1788/arch/arm/cpu/cortex-m3/config.mk
--- u-boot-2011.06/arch/arm/cpu/cortex-m3/config.mk	1969-12-31 16:00:00.000000000 -0800
+++ u-boot-2011.06-lpc1788/arch/arm/cpu/cortex-m3/config.mk	2011-08-12 11:20:52.763248321 -0700
@@ -0,0 +1,33 @@
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
+
+# Cortex M3 with thumb2 support
+PLATFORM_CPPFLAGS += -march=armv7-m -mthumb -Os -static-libgcc -fpic -mtune=cortex-m3 -nostdlib
+# =========================================================================
+#
+# Supply options according to compiler version
+#
+# =========================================================================
+PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,\
+		    $(call cc-option,-malignment-traps,))
diff -Naur u-boot-2011.06/arch/arm/cpu/cortex-m3/cpu.c u-boot-2011.06-lpc1788/arch/arm/cpu/cortex-m3/cpu.c
--- u-boot-2011.06/arch/arm/cpu/cortex-m3/cpu.c	1969-12-31 16:00:00.000000000 -0800
+++ u-boot-2011.06-lpc1788/arch/arm/cpu/cortex-m3/cpu.c	2011-08-16 12:01:32.063249196 -0700
@@ -0,0 +1,49 @@
+/*
+ * Copyright (C) 2011 by NXP Semiconductors
+ * All rights reserved.
+ *
+ * @Author: Kevin Wells
+ * @Descr: Cortex M3 CPU functions
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/hardware.h>
+#include <asm/system.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include "asm/arch-cortex-m3/cortex-m3.h"
+
+/*
+ * Cortex M3 reset at core
+ */
+void cm3_reset_cpu(ulong addr)
+{
+	unsigned long *paircr = (unsigned long *) CM3_AIRCR;
+
+	asm volatile ("dsb");
+	*paircr = (*paircr & (7 << 8)) | 1 << 2 | 0x5FA << 16;
+	asm volatile ("dsb");
+
+	while (1);
+}
+
+int cleanup_before_linux (void)
+{
+	return 0;
+}
diff -Naur u-boot-2011.06/arch/arm/cpu/cortex-m3/lpc17xx/clocks.c u-boot-2011.06-lpc1788/arch/arm/cpu/cortex-m3/lpc17xx/clocks.c
--- u-boot-2011.06/arch/arm/cpu/cortex-m3/lpc17xx/clocks.c	1969-12-31 16:00:00.000000000 -0800
+++ u-boot-2011.06-lpc1788/arch/arm/cpu/cortex-m3/lpc17xx/clocks.c	2011-07-29 14:11:20.833593835 -0700
@@ -0,0 +1,179 @@
+/*
+ * Copyright (C) 2011 by NXP Semiconductors
+ * All rights reserved.
+ *
+ * @Author: Kevin Wells
+ * @Descr: LPC17xx clock control driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/lpc17_regs.h>
+#include <asm/arch/lpc17_clocks.h>
+#include <asm/arch/lpc17_clock_checks.h>
+
+#if CONFIG_LPC17_PLL0_USE_EXTOSC==1
+#define LPC17_SYSCLK CONFIG_LPC17_OSC_RATE
+#else
+#define LPC17_SYSCLK LPC17_INTOSCRATE
+#endif
+
+unsigned long lpc17_get_pll0_rate(void)
+{
+#if CONFIG_LPC17_PLL0_ENABLE==0
+	return 0;
+#else
+	return LPC17_SYSCLK * CONFIG_LPC17_PLL0_M;
+#endif
+}
+
+unsigned long lpc17_get_pll1_rate(void)
+{
+#if CONFIG_LPC17_PLL1_ENABLE==0
+	return 0;
+#else
+	return CONFIG_LPC17_OSC_RATE * CONFIG_LPC17_PLL1_M;
+#endif
+}
+
+unsigned long lpc17_get_cpu_rate(void)
+{
+#if CONFIG_LPC17_PLL0_FOR_CPU==1
+	return lpc17_get_pll0_rate() / CONFIG_LPC17_CPU_DIV;
+#else
+	return LPC17_SYSCLK / CONFIG_LPC17_CPU_DIV;
+#endif
+}
+
+unsigned long lpc17_get_usb_rate(void)
+{
+	return lpc17_get_pll1_rate() / CONFIG_LPC17_USB_DIV;
+}
+
+unsigned long lpc17_get_emc_rate(void)
+{
+#if CONFIG_LPC17_PLL0_FOR_CPU==1
+	return lpc17_get_pll0_rate() / (1 + CONFIG_LPC17_EMC_HALFCPU);
+#else
+	return LPC17_SYSCLK / (1 + CONFIG_LPC17_EMC_HALFCPU);
+#endif
+}
+
+unsigned long lpc17_get_pclk_rate(void)
+{
+#if CONFIG_LPC17_PLL0_FOR_CPU==1
+	return lpc17_get_pll0_rate() / CONFIG_LPC17_PCLK_DIV;
+#else
+	return LPC17_SYSCLK / CONFIG_LPC17_PCLK_DIV;
+#endif
+}
+
+void lpc17_clk_enable(lpc17xx_clk clk, int enable)
+{
+	if (enable)
+		__raw_writel(__raw_readl(LPC17_SC_PCONP) | (1 << (int) clk),
+			LPC17_SC_PCONP);
+	else
+		__raw_writel(__raw_readl(LPC17_SC_PCONP) & ~(1 << (int) clk),
+			LPC17_SC_PCONP);
+}
+
+#if CONFIG_LPC17_PLL0_ENABLE==1
+static inline void lpc17_pll0_latch(long pllcon)
+{
+	__raw_writel(pllcon, LPC17_SC_PLL0CON);
+	__raw_writel(0xAA, LPC17_SC_PLL0FEED);
+	__raw_writel(0x55, LPC17_SC_PLL0FEED);
+}
+#endif
+
+#if CONFIG_LPC17_PLL1_ENABLE==1
+static inline void lpc17_pll1_latch(long pllcon)
+{
+	__raw_writel(pllcon, LPC17_SC_PLL1CON);
+	__raw_writel(0xAA, LPC17_SC_PLL1FEED);
+	__raw_writel(0x55, LPC17_SC_PLL1FEED);
+}
+#endif
+
+/*
+ * Sets up system clocking from the various CONFIG_ values in the
+ * u-boot board config file.
+ */
+void lpc17_setup_clocks(void)
+{
+	long reg;
+
+#if CONFIG_LPC17_PLL0_USE_EXTOSC==1
+	/* Enable oscillator and wait for it to become ready */
+#if CONFIG_LPC17_OSC_RATE > 15000000
+	__raw_writel(__raw_readl(LPC17_SC_SCS) | (1 << 5) | (1 << 4),
+		LPC17_SC_SCS);
+#else
+	__raw_writel(__raw_readl(LPC17_SC_SCS) | (1 << 5), LPC17_SC_SCS);
+#endif
+	while (!(__raw_readl(LPC17_SC_SCS) & (1 << 6)));
+
+	/* Switch PLL0 and SYSCLK to the external oscillator */
+	__raw_writel(0x1, LPC17_SC_CLKSRCSEL);
+#endif
+
+#if CONFIG_LPC17_PLL0_ENABLE==1
+	/* PLL0 setup */
+	__raw_writel((CONFIG_LPC17_PLL0_M - 1) | CONFIG_LPC17_PLL0_P << 5,
+		LPC17_SC_PLL0CFG);
+	lpc17_pll0_latch(1);
+
+	/* Wait for lock */
+	while (!(__raw_readl(LPC17_SC_PLL0STAT) & (1 << 10)));
+#endif
+
+#if CONFIG_LPC17_PLL1_ENABLE==1
+	/* PLL1 setup */
+	__raw_writel((CONFIG_LPC17_PLL1_M - 1) | CONFIG_LPC17_PLL1_P << 5,
+		LPC17_SC_PLL1CFG);
+	lpc17_pll1_latch(1);
+
+	/* Wait for lock */
+	while (!(__raw_readl(LPC17_SC_PLL1STAT) & (1 << 10)));
+#endif
+
+	/* CPU clock */
+#if CONFIG_LPC17_PLL0_FOR_CPU==1
+	__raw_writel((1 << 8) | CONFIG_LPC17_CPU_DIV, LPC17_SC_CCLKSEL);
+#else
+	__raw_writel(CONFIG_LPC17_CPU_DIV, LPC17_SC_CCLKSEL);
+#endif
+
+	/* USB clock */
+	__raw_writel((0x20 << 8) | CONFIG_LPC17_USB_DIV, LPC17_SC_USBCLKSEL);
+
+	/* EMC clock */
+	__raw_writel(CONFIG_LPC17_EMC_HALFCPU, LPC17_SC_EMCCLKSEL);
+
+	/* Peripheral clock */
+	__raw_writel(CONFIG_LPC17_PCLK_DIV, LPC17_SC_PCLKSEL);
+
+	/* Flash accelerator */
+	__raw_writel((CONFIG_LPC17_FLASH_CLOCKS - 1) << 12 | 0x3A,
+		LPC17_SC_FLASHCFG);
+
+	/* Setup CLKOUT for CPU rate divided by 16 */
+	__raw_writel(0 | 16 << 4 | 0x100, LPC17_SC_CLKOUTCFG);
+}
+
diff -Naur u-boot-2011.06/arch/arm/cpu/cortex-m3/lpc17xx/common.c u-boot-2011.06-lpc1788/arch/arm/cpu/cortex-m3/lpc17xx/common.c
--- u-boot-2011.06/arch/arm/cpu/cortex-m3/lpc17xx/common.c	1969-12-31 16:00:00.000000000 -0800
+++ u-boot-2011.06-lpc1788/arch/arm/cpu/cortex-m3/lpc17xx/common.c	2011-08-16 11:05:06.261931548 -0700
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2011 by NXP Semiconductors
+ * All rights reserved.
+ *
+ * @Author: Kevin Wells
+ * @Descr: LPC17xx common support functions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+
+#ifdef CONFIG_DISPLAY_CPUINFO
+/* Print CPU information */
+int print_cpuinfo(void)
+{
+	puts("NXP LPC1788 Cortex-M3\n");
+
+	return 0;
+}
+#endif	/* CONFIG_DISPLAY_CPUINFO */
+
diff -Naur u-boot-2011.06/arch/arm/cpu/cortex-m3/lpc17xx/flash.c u-boot-2011.06-lpc1788/arch/arm/cpu/cortex-m3/lpc17xx/flash.c
--- u-boot-2011.06/arch/arm/cpu/cortex-m3/lpc17xx/flash.c	1969-12-31 16:00:00.000000000 -0800
+++ u-boot-2011.06-lpc1788/arch/arm/cpu/cortex-m3/lpc17xx/flash.c	2011-08-16 11:49:41.070124652 -0700
@@ -0,0 +1,238 @@
+/*
+ * Copyright (C) 2011 by NXP Semiconductors
+ * All rights reserved.
+ *
+ * @Author: Kevin Wells
+ * @Descr: LPC17xx FLASH support for u-boot
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/arch/lpc17_iaplib.h>
+#include <asm/arch/lpc17_clocks.h>
+
+/*
+ * Note this driver uses a small 256 byte region at the start of IRAM for
+ * loacl buffer storage.
+ */
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+static const lpc17_iap_block_list *pbl;
+
+/*
+ * Initialize FLASH
+ */
+ulong flash_init (void)
+{
+	int i, mb;
+
+	/* Clock in is CPU in KHz */
+	lpc17_iap_init(lpc17_get_cpu_rate() / 1000);
+	mb = lpc17_iap_get_sectors();
+
+	if (mb > CONFIG_SYS_MAX_FLASH_SECT) {
+		printf("CONFIG_SYS_MAX_FLASH_SECT too small (%d)!\n",
+			CONFIG_SYS_MAX_FLASH_SECT);
+		printf("%d sectors detected\n", mb);
+		return 0;
+	}
+
+	/* Only 1 bank with multiple sectors */
+	flash_info[0].size = lpc17_iap_get_size();
+	flash_info[0].flash_id = lpc17_iap_read_part_id_num() &
+		FLASH_VENDMASK;
+	flash_info[0].sector_count = lpc17_iap_get_sectors();
+	memset(flash_info[0].protect, 0, mb);
+
+	pbl = lpc17_iap_get_block_list();
+	for (i = 0; i < mb; i++) {
+		flash_info[0].start[i] = CONFIG_SYS_FLASH_BASE +
+			pbl[i].offset;
+	}
+
+	return lpc17_iap_get_size();
+}
+
+/*
+ * Display FLASH info
+ */
+void flash_print_info (flash_info_t *info)
+{
+	int i;
+	unsigned long sn[4];
+
+	printf("NXP LPC17xx internal FLASH\n");
+
+	printf ("  %ld KB in %d Sectors\n", info->size >> 10,
+		info->sector_count);
+
+	printf ("  LPC17 Part ID: %08x\n",
+		(int) lpc17_iap_read_part_id_num());
+
+	lpc17_iap_read_serial_num(sn);
+	printf ("  LPC17 Unique ID: %08x%08x%08x%08x\n", (int) sn[0],
+		(int) sn[1], (int) sn[2], (int) sn[3]);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; i++) {
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+		printf (" %08lX%s", info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+}
+
+/*
+ * Erase FLASH sectors
+ */
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	unsigned long badaddr, baddata;
+	unsigned long first = (unsigned long) s_first;
+	unsigned long last = (unsigned long) s_last;
+
+	if ((first < 0) || (first >= flash_info[0].sector_count) ||
+		(last < first) || (last >= flash_info[0].sector_count)) {
+		printf("Invalid sector range, allowed 0 to %d\n",
+			flash_info[0].sector_count - 1);
+		return ERR_NOT_ERASED;
+	}
+
+	printf ("Erasing %d sectors starting at sector %2d.\n",
+		s_last - s_first + 1, s_first);
+
+	if (lpc17_iap_prepare_sectors(first, last) != iap_cmd_success) {
+		printf("Error perparing erase\n");
+		return ERR_NOT_ERASED;
+	}
+
+	if (lpc17_iap_erase_sectors(first, last) != iap_cmd_success) {
+		printf("Error erasing FLASH\n");
+		return ERR_NOT_ERASED;
+	}
+
+	if (lpc17_iap_blank_check_sectors(first, last, &badaddr, &baddata) ==
+		iap_sector_not_blank) {
+		printf("Error validating erase\n");
+		return ERR_NOT_ERASED;
+	}
+
+	return ERR_OK;
+}
+
+static unsigned long find_sector(unsigned long address) {
+	int i = 0;
+
+	while (i < flash_info[0].sector_count) {
+		if ((address >= flash_info[0].start[i]) &&
+			(address < (flash_info[0].start[i] + pbl[i].size)))
+			return (unsigned long) i;
+		else
+			i++;
+	}
+
+	return -1;
+}
+
+/*
+ * Copy memory buffer to FLASH
+ */
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	uchar *pdst, *psrc;
+	ulong bytes = cnt;
+	unsigned long sect;
+	lpc17_iap_status st;
+	void *ilcl = (void *) 0x10000000;
+
+	/* Write size must be on a 256 byte boundary */
+	if (cnt % 256) {
+		printf ("FLASH destination address must be 256 byte "
+			"aligned\n");
+		return ERR_PROG_ERROR;
+	}
+
+	if (((ulong) addr % 256) != 0) {
+		printf ("Destination address must be 256 byte aligned\n");
+		return ERR_PROG_ERROR;
+	}
+
+	if (((ulong) src & 0x3) != 0) {
+		printf ("Source address must be 32-bit aligned\n");
+		return ERR_PROG_ERROR;
+	}
+
+	if (addr > flash_info[0].size - cnt) {
+		printf ("Write range exceeds end of FLASH\n");
+		return ERR_PROG_ERROR;
+	}
+
+	/* Check that area is erased */
+	pdst = (uchar *) addr;
+	while (bytes-- > 0) {
+		if (*pdst != 0xFF) {
+			printf("FLASH is not blank\n");
+			return ERR_NOT_ERASED;
+		}
+
+		pdst++;
+	}
+
+	bytes = cnt;
+	pdst = (uchar *) addr;
+	psrc = src;
+
+	printf("Writing %d bytes from %x from %x, please be patient...\n",
+		(int) bytes, (unsigned int) src, (unsigned int) addr);
+
+	/* Write data in 256 byte chunks */
+	while (bytes > 0) {
+		sect = find_sector(addr);
+
+		if (lpc17_iap_prepare_sectors(sect, sect) !=
+			iap_cmd_success) {
+			printf ("Error preparing FLASH for word write\n");
+			return ERR_PROG_ERROR;
+		}
+
+		/* Copy RAM to FLASH */
+		memcpy(ilcl, (void *) src, 256);
+		st = lpc17_iap_ram_to_flash(addr, (unsigned long ) ilcl, 256);
+		if (st != iap_cmd_success) {
+			printf ("Error writing word to FLASH (%d)\n", st);
+			return ERR_PROG_ERROR;
+		}
+
+		bytes -= 256;
+		src += 256;
+		addr += 256;
+	}
+
+	/* Verify */
+	while (cnt-- > 0) {
+		if (*psrc != *pdst) {
+			printf ("Write error in FLASH validation\n");
+			return ERR_PROG_ERROR;
+		}
+
+		psrc++;
+		pdst++;
+	}
+
+	return 0;
+}
diff -Naur u-boot-2011.06/arch/arm/cpu/cortex-m3/lpc17xx/gpio.c u-boot-2011.06-lpc1788/arch/arm/cpu/cortex-m3/lpc17xx/gpio.c
--- u-boot-2011.06/arch/arm/cpu/cortex-m3/lpc17xx/gpio.c	1969-12-31 16:00:00.000000000 -0800
+++ u-boot-2011.06-lpc1788/arch/arm/cpu/cortex-m3/lpc17xx/gpio.c	2011-08-12 16:40:08.420787102 -0700
@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) 2011 by NXP Semiconductors
+ * All rights reserved.
+ *
+ * @Author: Kevin Wells
+ * @Descr: LPC17xx GPIO functions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/lpc17_regs.h>
+#include <asm/arch/lpc17_gpio.h>
+
+/* Set a GPIO as an input */
+void lpc17xx_gpio_set_input(unsigned char grp, unsigned char pin)
+{
+	unsigned long gd;
+
+	gd = __raw_readl(LPC17_FIODIR(grp));
+	gd &= ~(1 << pin);
+	__raw_writel(gd, LPC17_FIODIR(grp));
+}
+
+/* Set a GPIO as an output */
+void lpc17xx_gpio_set_output(unsigned char grp, unsigned char pin)
+{
+	unsigned long gd;
+
+	gd = __raw_readl(LPC17_FIODIR(grp));
+	gd |= (1 << pin);
+	__raw_writel(gd, LPC17_FIODIR(grp));
+}
+
+/* Set a output GPIO to a specific state */
+void lpc17xx_gpio_set_state(unsigned char grp, unsigned char pin, int st)
+{
+	if (st)
+		__raw_writel((1 << pin), LPC17_FIOSET(grp));
+	else
+		__raw_writel((1 << pin), LPC17_FIOCLR(grp));
+}
+
+/* Return the state of an input GPIO */
+int lpc17xx_gpio_get_state(unsigned char grp, unsigned char pin)
+{
+	return ((__raw_readl(LPC17_FIOPIN(grp)) & (1 << pin)) != 0);
+}
+
diff -Naur u-boot-2011.06/arch/arm/cpu/cortex-m3/lpc17xx/iaplib.c u-boot-2011.06-lpc1788/arch/arm/cpu/cortex-m3/lpc17xx/iaplib.c
--- u-boot-2011.06/arch/arm/cpu/cortex-m3/lpc17xx/iaplib.c	1969-12-31 16:00:00.000000000 -0800
+++ u-boot-2011.06-lpc1788/arch/arm/cpu/cortex-m3/lpc17xx/iaplib.c	2011-08-15 17:34:47.770821720 -0700
@@ -0,0 +1,264 @@
+/*
+ * Copyright (C) 2011 by NXP Semiconductors
+ * All rights reserved.
+ *
+ * @Author: Kevin Wells
+ * @Descr: LPC17xx FLASH IAP interface library
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <asm/arch/lpc17_iaplib.h>
+
+/* IAP function pointer */
+#define IAP_LOCATION	0x1FFF1FF1
+typedef void (*lpc178x_iap) (unsigned long *, unsigned long *);
+static lpc178x_iap lpc178x_iap_entry;
+
+/* IAP commands */
+typedef enum {
+	iap_cmd_prep_sectors = 50,
+	iap_cmd_ram_to_flash,
+	iap_cmd_erase_sectors,
+	iap_cmd_blank_check_sectors,
+	iap_cmd_read_part_id,
+	iap_cmd_read_boot_code_version,
+	iap_cmd_read_device_sn,
+	iap_cmd_compare,
+	iap_cmd_reinvoke_isp
+} iap_command;
+
+static unsigned long iap_num_sectors;
+static unsigned long iap_flash_size;
+static unsigned long iap_clkrate; /* In KHz */
+
+static const lpc17_iap_block_list iap_blocks[] = {
+	{0x00000000, 0x00001000},
+	{0x00001000, 0x00001000},
+	{0x00002000, 0x00001000},
+	{0x00003000, 0x00001000},
+	{0x00004000, 0x00001000},
+	{0x00005000, 0x00001000},
+	{0x00006000, 0x00001000},
+	{0x00007000, 0x00001000}, /* 32K part ends here */
+	{0x00008000, 0x00001000},
+	{0x00009000, 0x00001000},
+	{0x0000A000, 0x00001000},
+	{0x0000B000, 0x00001000},
+	{0x0000C000, 0x00001000},
+	{0x0000D000, 0x00001000},
+	{0x0000E000, 0x00001000},
+	{0x0000F000, 0x00001000}, /* 64K part ends here */
+	{0x00010000, 0x00008000},
+	{0x00018000, 0x00008000}, /* 128K part ends here */
+	{0x00020000, 0x00008000},
+	{0x00028000, 0x00008000},
+	{0x00030000, 0x00008000},
+	{0x00038000, 0x00008000}, /* 256K part ends here */
+	{0x00040000, 0x00008000},
+	{0x00048000, 0x00008000},
+	{0x00050000, 0x00008000},
+	{0x00058000, 0x00008000},
+	{0x00060000, 0x00008000},
+	{0x00068000, 0x00008000},
+	{0x00070000, 0x00008000},
+	{0x00078000, 0x00008000} /* 512K part ends here */
+};
+
+/* Device specific ID coding (information only) */
+#define LPC1774_DEVID	0x27011132
+#define LPC1776_DEVID	0x27191F43
+#define LPC1777_DEVID	0x27193747
+#define LPC1778_DEVID	0x27193F47
+#define LPC1785_DEVID	0x281D1743
+#define LPC1786_DEVID	0x281D1F43
+#define LPC1787_DEVID	0x281D3747
+#define LPC1788_DEVID	0x281D3F47
+
+static unsigned long iap_commands[5];
+static unsigned long iap_results[5];
+
+/* Return the number of sectors */
+unsigned long lpc17_iap_get_sectors(void)
+{
+	return iap_num_sectors;
+}
+
+/* Return the FLASH size */
+unsigned long lpc17_iap_get_size(void)
+{
+	return iap_flash_size;
+}
+
+/* Return a list of block addresses and sizes */
+const lpc17_iap_block_list *lpc17_iap_get_block_list(void)
+{
+	return iap_blocks;
+}
+
+/* Prepare sectors for erase or write */
+lpc17_iap_status lpc17_iap_prepare_sectors(unsigned long start,
+	unsigned long end)
+{
+	iap_commands[0] = iap_cmd_prep_sectors;
+	iap_commands[1] = start;
+	iap_commands[2] = end;
+
+	lpc178x_iap_entry(iap_commands, iap_results);
+
+	return iap_results[0];
+}
+
+/* Copy RAM to FLASH */
+lpc17_iap_status lpc17_iap_ram_to_flash(unsigned long dst, unsigned long src,
+	unsigned long bytes)
+{
+	iap_commands[0] = iap_cmd_ram_to_flash;
+	iap_commands[1] = dst;
+	iap_commands[2] = src;
+	iap_commands[3] = bytes;
+	iap_commands[4] = iap_clkrate;
+
+	lpc178x_iap_entry(iap_commands, iap_results);
+
+	return iap_results[0];
+}
+
+/* Erase sectors */
+lpc17_iap_status lpc17_iap_erase_sectors(unsigned long start,
+	unsigned long end)
+{
+	iap_commands[0] = iap_cmd_erase_sectors;
+	iap_commands[1] = start;
+	iap_commands[2] = end;
+	iap_commands[3] = iap_clkrate;
+
+	lpc178x_iap_entry(iap_commands, iap_results);
+
+	return iap_results[0];
+}
+
+/* Blank check sectors */
+lpc17_iap_status lpc17_iap_blank_check_sectors(unsigned long start,
+	unsigned long end, unsigned long *bad_addr, unsigned long *bad_data)
+{
+	iap_commands[0] = iap_cmd_blank_check_sectors;
+	iap_commands[1] = start;
+	iap_commands[2] = end;
+	iap_commands[3] = iap_clkrate;
+
+	lpc178x_iap_entry(iap_commands, iap_results);
+
+	*bad_addr = iap_results[1];
+	*bad_data = iap_results[2];
+
+	return iap_results[0];
+}
+
+/* Read part identification number */
+unsigned long lpc17_iap_read_part_id_num(void)
+{
+	iap_commands[0] = iap_cmd_read_part_id;
+
+	lpc178x_iap_entry(iap_commands, iap_results);
+
+	return iap_results[1];
+}
+
+/* Read boot code version */
+unsigned long lpc17_iap_read_boot_code_version(void)
+{
+	iap_commands[0] = iap_cmd_read_boot_code_version;
+
+	lpc178x_iap_entry(iap_commands, iap_results);
+
+	return iap_results[1] & 0xFFFF;
+}
+
+/* Read device serial number */
+void lpc17_iap_read_serial_num(unsigned long sn[4])
+{
+	iap_commands[0] = iap_cmd_read_device_sn;
+
+	lpc178x_iap_entry(iap_commands, iap_results);
+}
+
+/* Compare data */
+lpc17_iap_status iap_compare(unsigned long dst, unsigned long src,
+	unsigned long bytes, unsigned long *mis_addr)
+{
+	iap_commands[0] = iap_cmd_compare;
+	iap_commands[1] = dst;
+	iap_commands[2] = src;
+	iap_commands[3] = bytes;
+
+	lpc178x_iap_entry(iap_commands, iap_results);
+
+	*mis_addr = iap_results[1];
+
+	return iap_results[0];
+}
+
+/* Re-invoke ISP */
+void lpc17_iap_reinvoke_isp(void)
+{
+	iap_commands[0] = iap_cmd_reinvoke_isp;
+
+	/* Doesn't return */
+	lpc178x_iap_entry(iap_commands, iap_results);
+}
+
+/* Initialize IAP library - call this first */
+void lpc17_iap_init(unsigned clkrate)
+{
+	unsigned long val;
+
+	iap_clkrate = clkrate;
+
+	lpc178x_iap_entry = (lpc178x_iap) IAP_LOCATION;
+
+	/* Read part ID first to determine size of FLASH */
+	val = lpc17_iap_read_part_id_num();
+
+	/* Decode part ID to get number of sectors and size */
+	if ((val & 0x08000000) != 0) {
+		/* LPC178x */
+		if ((val & 0x00000004) != 0) {
+			/* LPC1787, LPC1788 */
+			iap_flash_size = 512 * 1024;
+			iap_num_sectors = 30;
+		} else {
+			/* LPC1785, LPC1786 */
+			iap_flash_size = 256 * 1024;
+			iap_num_sectors = 22;
+		}
+	} else {
+		/* LPC177x */
+		if ((val & 0x00000004) != 0) {
+			/* LPC1777, LPC1778 */
+			iap_flash_size = 512 * 1024;
+			iap_num_sectors = 30;
+		} else if ((val & 0x00000002) != 0) {
+			/* LPC1776 */
+			iap_flash_size = 256 * 1024;
+			iap_num_sectors = 22;
+		} else {
+			/* LPC1774 */
+			iap_flash_size = 128 * 1024;
+			iap_num_sectors = 18;
+		}
+	}
+}
+
diff -Naur u-boot-2011.06/arch/arm/cpu/cortex-m3/lpc17xx/iocon.c u-boot-2011.06-lpc1788/arch/arm/cpu/cortex-m3/lpc17xx/iocon.c
--- u-boot-2011.06/arch/arm/cpu/cortex-m3/lpc17xx/iocon.c	1969-12-31 16:00:00.000000000 -0800
+++ u-boot-2011.06-lpc1788/arch/arm/cpu/cortex-m3/lpc17xx/iocon.c	2011-07-27 09:11:18.574284348 -0700
@@ -0,0 +1,91 @@
+/*
+ * Copyright (C) 2011 by NXP Semiconductors
+ * All rights reserved.
+ *
+ * @Author: Kevin Wells
+ * @Descr: LPC17xx IOCON setup support functions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/lpc17_regs.h>
+#include <asm/arch/lpc17_iocon.h>
+
+typedef struct {
+	u16 grp		: 3;
+	u16 pin_start	: 5;
+	u16 pin_end	: 5;
+	LPC17_IOCON_TYPE iocon_type;
+} LPC17_IOCON_RANGE;
+
+/* Set the configuration of a IOCON pin */
+void lpc17_iocon_setup(iocon_pin_type *iocon_pin)
+{
+	u32 regval;
+
+	switch (iocon_pin->iocon_type)
+	{
+	case IOCON_D_TYPE:
+		regval = (u32) (iocon_pin->iocon.d.func |
+			(iocon_pin->iocon.d.mode << 3) |
+			(iocon_pin->iocon.d.hys << 5) |
+			(iocon_pin->iocon.d.inv << 6) | 
+			(iocon_pin->iocon.d.slew << 9) |
+			(iocon_pin->iocon.d.od << 10));
+		break;
+
+	case IOCON_A_TYPE:
+		regval = (u32) (iocon_pin->iocon.a.func |
+			(iocon_pin->iocon.a.mode << 3) |
+			(iocon_pin->iocon.a.hys << 5) |
+			(iocon_pin->iocon.a.inv << 6) | 
+			(iocon_pin->iocon.a.admode << 7) | 
+			(iocon_pin->iocon.a.inv << 6) | 
+			(iocon_pin->iocon.a.filter << 8) |
+			(iocon_pin->iocon.a.od << 10) |
+			(iocon_pin->iocon.a.dacen << 11));
+		break;
+
+	case IOCON_U_TYPE:
+		regval = (u32) iocon_pin->iocon.u.func;
+		break;
+
+	case IOCON_I_TYPE:
+		regval = (u32) (iocon_pin->iocon.i.func |
+			(iocon_pin->iocon.i.inv << 6) |
+			(iocon_pin->iocon.i.hs << 8) |
+			(iocon_pin->iocon.i.hidrive << 9));
+		break;
+
+	case IOCON_W_TYPE:
+		regval = (u32) (iocon_pin->iocon.w.func |
+			(iocon_pin->iocon.w.mode << 3) |
+			(iocon_pin->iocon.w.hys << 5) |
+			(iocon_pin->iocon.w.inv << 6) | 
+			(iocon_pin->iocon.w.filter << 8) |
+			(iocon_pin->iocon.w.slew << 9) |
+			(iocon_pin->iocon.w.od << 10));
+		break;
+
+	default:
+		return;
+	}
+
+	__raw_writel(regval, LPC17_IOCON(iocon_pin->grp, iocon_pin->pin));
+}
+
diff -Naur u-boot-2011.06/arch/arm/cpu/cortex-m3/lpc17xx/Makefile u-boot-2011.06-lpc1788/arch/arm/cpu/cortex-m3/lpc17xx/Makefile
--- u-boot-2011.06/arch/arm/cpu/cortex-m3/lpc17xx/Makefile	1969-12-31 16:00:00.000000000 -0800
+++ u-boot-2011.06-lpc1788/arch/arm/cpu/cortex-m3/lpc17xx/Makefile	2011-08-15 10:27:14.920713372 -0700
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000-2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(SOC).o
+
+COBJS	= timer.o clocks.o serial.o common.o iaplib.o iocon.o gpio.o
+COBJS	+= flash.o
+SOBJS	= 
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
+
+all:	$(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff -Naur u-boot-2011.06/arch/arm/cpu/cortex-m3/lpc17xx/serial.c u-boot-2011.06-lpc1788/arch/arm/cpu/cortex-m3/lpc17xx/serial.c
--- u-boot-2011.06/arch/arm/cpu/cortex-m3/lpc17xx/serial.c	1969-12-31 16:00:00.000000000 -0800
+++ u-boot-2011.06-lpc1788/arch/arm/cpu/cortex-m3/lpc17xx/serial.c	2011-07-27 15:36:17.723357886 -0700
@@ -0,0 +1,128 @@
+/*
+ * Copyright (C) 2011 by NXP Semiconductors
+ * All rights reserved.
+ *
+ * @Author: Kevin Wells
+ * @Descr: LPC17xx serial port functions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/lpc17_regs.h>
+#include <asm/arch/lpc17_clocks.h>
+
+#if CONFIG_LPC17_UART_BOOT == 0
+#define UART_BASE LPC17_UART0
+#define UART_CLK LPC17_CLK_UART0
+#endif
+#if CONFIG_LPC17_UART_BOOT == 1
+#define UART_BASE LPC17_UART1
+#define UART_CLK LPC17_CLK_UART1
+#endif
+#if CONFIG_LPC17_UART_BOOT == 2
+#define UART_BASE LPC17_UART2
+#define UART_CLK LPC17_CLK_UART2
+#endif
+#if CONFIG_LPC17_UART_BOOT == 3
+#define UART_BASE LPC17_UART3
+#define UART_CLK LPC17_CLK_UART3
+#endif
+#if CONFIG_LPC17_UART_BOOT == 4
+#define UART_BASE LPC17_UART4
+#define UART_CLK LPC17_CLK_UART4
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void serial_setbrg(void)
+{
+	long div, clkrate;
+
+	clkrate = lpc17_get_pclk_rate();
+	div = clkrate / (gd->baudrate * 16);
+
+	__raw_writel(__raw_readl(LPC17_UART_LCR(UART_BASE)) | 0x80,
+		LPC17_UART_LCR(UART_BASE));
+	__raw_writel(div & 0xFF, LPC17_UART_FIFO_DLL(UART_BASE));
+	__raw_writel((div >> 8) & 0xFF, LPC17_UART_IER_DLM(UART_BASE));
+	__raw_writel(__raw_readl(LPC17_UART_LCR(UART_BASE)) & ~0x80,
+		LPC17_UART_LCR(UART_BASE));
+}
+
+/*
+ * it is the responsiblity of the board code to setup the proper pin
+ * muxing for the selected UART
+ */
+int serial_init(void)
+{
+	volatile unsigned int tmp32;
+
+	/* Enable UART clock */
+	lpc17_clk_enable(UART_CLK, 1);
+
+	/* set baudrate */
+	gd->baudrate = CONFIG_BAUDRATE;
+	serial_setbrg();
+
+	/* Setup default UART state for N81 with FIFO mode */
+	__raw_writel(0x3, LPC17_UART_LCR(UART_BASE));
+
+	/* Clear FIFOs and set FIFO level */
+	__raw_writel(0x7, LPC17_UART_FCR_IIR(UART_BASE));
+	tmp32 = __raw_readl(LPC17_UART_FCR_IIR(UART_BASE));
+	tmp32 = __raw_readl(LPC17_UART_LSR(UART_BASE));
+
+	return 0;
+}
+
+int serial_getc(void)
+{
+	/* Wait for a character from the UART */
+	while (!(__raw_readl(LPC17_UART_LSR(UART_BASE)) & (1 << 0)));
+
+	return (int) (__raw_readl(LPC17_UART_FIFO_DLL(UART_BASE)) & 0xFF);
+}
+
+void serial_putc(const char c)
+{
+	/* Wait for FIFO to become empty */
+	while (!(__raw_readl(LPC17_UART_LSR(UART_BASE)) & (1 << 5)));
+
+	__raw_writel((long) c, LPC17_UART_FIFO_DLL(UART_BASE));
+
+	/* If \n, also do \r */
+	if (c == '\n')
+		serial_putc('\r');
+}
+
+int serial_tstc(void)
+{
+	/* Test for a character from the UART */
+	if (!(__raw_readl(LPC17_UART_LSR(UART_BASE)) & 1))
+		return 0;
+
+	return 1;
+}
+
+void serial_puts(const char *s)
+{
+	while (*s)
+		serial_putc (*s++);
+}
+
diff -Naur u-boot-2011.06/arch/arm/cpu/cortex-m3/lpc17xx/timer.c u-boot-2011.06-lpc1788/arch/arm/cpu/cortex-m3/lpc17xx/timer.c
--- u-boot-2011.06/arch/arm/cpu/cortex-m3/lpc17xx/timer.c	1969-12-31 16:00:00.000000000 -0800
+++ u-boot-2011.06-lpc1788/arch/arm/cpu/cortex-m3/lpc17xx/timer.c	2011-08-16 13:11:48.171374308 -0700
@@ -0,0 +1,114 @@
+/*
+ * Copyright (C) 2011 by NXP Semiconductors
+ * All rights reserved.
+ *
+ * @Author: Kevin Wells
+ * @Descr: LPC17xx timer driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/lpc17_regs.h>
+#include <asm/arch/lpc17_clocks.h>
+
+#define TIMER_CLK LPC17_CLK_TIM0
+#define UDELAY_CLK LPC17_CLK_TIM1
+#define TIMER_BASE LPC17_TIMER0
+#define UDELAY_BASE LPC17_TIMER1
+
+void reset_timer(void)
+{
+	unsigned int clkdlycnt, tbaseclk;
+
+	/* Reset timer */
+	__raw_writel(2, LPC17_TIMER_TCR(TIMER_BASE));
+	__raw_writel(0, LPC17_TIMER_TCR(TIMER_BASE));
+	__raw_writel(0, LPC17_TIMER_TC(TIMER_BASE));
+
+	/* Clear and enable match function */
+	__raw_writel(1, LPC17_TIMER_IR(TIMER_BASE));
+
+	/* Count mode is PCLK edge */
+	__raw_writel(0, LPC17_TIMER_CTCR(TIMER_BASE));
+
+	/* Set prescale counter */
+	tbaseclk = lpc17_get_pclk_rate();
+	clkdlycnt = (tbaseclk / CONFIG_SYS_HZ);
+	__raw_writel(clkdlycnt, LPC17_TIMER_PR(TIMER_BASE));
+
+	/* Enable the timer */
+	__raw_writel(1, LPC17_TIMER_TCR(TIMER_BASE));
+}
+
+ulong get_timer(ulong base)
+{
+	ulong tcr = __raw_readl(LPC17_TIMER_TC(TIMER_BASE));
+	return tcr - base;
+}
+
+void __udelay(unsigned long usec)
+{
+	long tbaseclk;
+
+	/* Enable timer system clock */
+	lpc17_clk_enable(UDELAY_CLK, 1);
+
+	/* Reset timer */
+	__raw_writel(2, LPC17_TIMER_TCR(UDELAY_BASE));
+	__raw_writel(0, LPC17_TIMER_TCR(UDELAY_BASE));
+	__raw_writel(0, LPC17_TIMER_PC(UDELAY_BASE));
+	__raw_writel(0, LPC17_TIMER_PR(UDELAY_BASE));
+
+	/* Clear and enable match function */
+	__raw_writel(1, LPC17_TIMER_IR(UDELAY_BASE));
+
+	/* Count mode is PCLK edge */
+	__raw_writel(0, LPC17_TIMER_CTCR(UDELAY_BASE));
+
+	/* Set prescale counter value for proper tick rate */
+	tbaseclk = lpc17_get_pclk_rate();
+	tbaseclk = (tbaseclk / 1000000) - 1;
+	__raw_writel(tbaseclk, LPC17_TIMER_PR(UDELAY_BASE));
+
+	/* Set match for number of usecs */
+	__raw_writel(usec, LPC17_TIMER_MR0(UDELAY_BASE));
+
+	/* Interrupt on match 0 */
+	__raw_writel(1, LPC17_TIMER_MCR(UDELAY_BASE));
+
+	/* Enable the timer */
+	__raw_writel(1, LPC17_TIMER_TCR(UDELAY_BASE));
+
+	/* Loop until match occurs */
+	while (!(__raw_readl(LPC17_TIMER_IR(UDELAY_BASE)) & 0x1));
+
+	/* Stop timer */
+	__raw_writel(0, LPC17_TIMER_TCR(UDELAY_BASE));
+
+	/* Disable timer system clock */
+	lpc17_clk_enable(UDELAY_CLK, 0);
+}
+
+int timer_init(void)
+{
+	lpc17_clk_enable(TIMER_CLK, 1);
+	reset_timer();
+
+	return 0;
+}
+
diff -Naur u-boot-2011.06/arch/arm/cpu/cortex-m3/Makefile u-boot-2011.06-lpc1788/arch/arm/cpu/cortex-m3/Makefile
--- u-boot-2011.06/arch/arm/cpu/cortex-m3/Makefile	1969-12-31 16:00:00.000000000 -0800
+++ u-boot-2011.06-lpc1788/arch/arm/cpu/cortex-m3/Makefile	2011-08-16 09:40:40.020125213 -0700
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(CPU).o
+
+START	:= start.o
+COBJS	:= cpu.o nvic.o mpu.o
+
+SRCS	:= $(START:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+START	:= $(addprefix $(obj),$(START))
+
+all:	$(obj).depend $(START) $(LIB)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff -Naur u-boot-2011.06/arch/arm/cpu/cortex-m3/mpu.c u-boot-2011.06-lpc1788/arch/arm/cpu/cortex-m3/mpu.c
--- u-boot-2011.06/arch/arm/cpu/cortex-m3/mpu.c	1969-12-31 16:00:00.000000000 -0800
+++ u-boot-2011.06-lpc1788/arch/arm/cpu/cortex-m3/mpu.c	2011-08-16 13:51:42.931318037 -0700
@@ -0,0 +1,66 @@
+/*
+ * Copyright (C) 2011 by NXP Semiconductors
+ * All rights reserved.
+ *
+ * @Author: Kevin Wells
+ * @Descr: Cortex M3 MPU initialization code
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include "asm/arch-cortex-m3/cortex-m3.h"
+
+static void cm3_add_mpu_region(unsigned long region, unsigned long address,
+	unsigned long control)
+{
+	volatile unsigned long *pmpu = (unsigned long *) CM3_MPU_REGBASE;
+
+	*(pmpu + 2) = region;
+	*(pmpu + 3) = address;
+	*(pmpu + 4) = control;
+	*(pmpu + 4) = control | 0x1;
+}
+
+void mpu_init(const unsigned long *init_table)
+{
+	unsigned long rbar, region = 0;
+
+	if (init_table == (unsigned long *) 0x00000000) {
+		/* Open all of memory */
+		cm3_add_mpu_region(0, 0x00000000, CM3_MPU_DATA_RW_RW |
+			CM3_MPU_SIZE_4GB | CM3_MPU_ENABLE);
+	} else {
+		/* Use passed table */
+		while (*init_table != 0xFFFFFFFF) {
+			rbar = *init_table;
+			rbar |= region | (1 << 4);
+			cm3_add_mpu_region(region, rbar,
+				*(init_table + 1));
+			init_table += 2;
+			region++;
+		}
+	}
+}
+
+void mpu_enable(int enable)
+{
+	unsigned long *pmpu = (unsigned long *) CM3_MPU_REGBASE;
+
+	if (enable)
+		*(pmpu + 1) = 0x7;
+	else
+		*(pmpu + 1) = 0x0;
+}
+
diff -Naur u-boot-2011.06/arch/arm/cpu/cortex-m3/nvic.c u-boot-2011.06-lpc1788/arch/arm/cpu/cortex-m3/nvic.c
--- u-boot-2011.06/arch/arm/cpu/cortex-m3/nvic.c	1969-12-31 16:00:00.000000000 -0800
+++ u-boot-2011.06-lpc1788/arch/arm/cpu/cortex-m3/nvic.c	2011-07-22 13:40:28.614584963 -0700
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2011 by NXP Semiconductors
+ * All rights reserved.
+ *
+ * @Author: Kevin Wells
+ * @Descr: Cortex M3 CPU NVIC support
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* Placeholder only for BVIC support and u-boot IRQ support */
+#ifdef CONFIG_USE_IRQ
+#error Cortex M3 NVIC support for IRQs not implemented
+#endif
+
diff -Naur u-boot-2011.06/arch/arm/cpu/cortex-m3/start.S u-boot-2011.06-lpc1788/arch/arm/cpu/cortex-m3/start.S
--- u-boot-2011.06/arch/arm/cpu/cortex-m3/start.S	1969-12-31 16:00:00.000000000 -0800
+++ u-boot-2011.06-lpc1788/arch/arm/cpu/cortex-m3/start.S	2011-08-16 14:11:56.250123550 -0700
@@ -0,0 +1,301 @@
+/*
+ * Copyright (C) 2011 by NXP Semiconductors
+ * All rights reserved.
+ *
+ * @Author: Kevin Wells
+ * @Descr: armboot - Startup Code for Cortex M3 (Boot from 0x0 only)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * This code always assumes it's running from address 0x0.
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <version.h>
+
+.extern	lpc17_board_init
+.extern red_LED_on
+.extern red_LED_off
+.extern udelay
+.extern mpu_init
+.extern mpu_enable
+#ifdef CONFIG_USE_BOARD_MPU_TABLE
+.extern board_mpu_table
+#endif
+
+/*************************************************************************
+ *
+ * M3 vector table and reset
+ *
+ * The M3 uses a small structure that contains the initial stack pointer,
+ * reset vector, NMI ISR vector, and hard fault vector. This structure is
+ * read at reset and used to jump to the reset code, setup the initial
+ * stack, and setup the NMI and hard fault ISR vectors in the NVIC.
+ *
+ *************************************************************************/
+	.globl _start
+_start:
+	.word	CONFIG_SYS_INIT_SP_ADDR
+	.word	(reset - _start) | 0x1
+	.word	(nmitrap_handler - _start) | 0x1
+	.word	(hardfault_handler - _start) | 0x1
+	.word	(mpufault_handler - _start) | 0x1
+	.word	(busfault_handler - _start) | 0x1
+	.word	(usagefault_handler - _start) | 0x1
+
+/*
+ * This word is the checksum of the first 7 words. After u-boot is built,
+ * run lpc17_fcg on the binary to compute and insert the checksum into
+ * the binary image. Be sure it's inserted before making the hex file
+ * for burning into FLASH.
+ */
+	.word	0 
+
+/*
+ * 5 more CM3 reserved vectors
+ */
+	.word 0, 0, 0, 0, 0
+
+/*
+ * Up to 64 device specific vectors
+ */
+	.rept 64
+	.word 0
+	.endr
+
+/*************************************************************************
+ *
+ * Various traps
+ *
+ * Early crashes prior to code execution in DRAM may not work
+ *
+ *************************************************************************/
+nmitrap_handler:
+	ldr	r0, =1000*1000/20 /* About 10Hz */
+	B	deadloop_toggle_led
+hardfault_handler:
+	ldr	r0, =1000*1000/10 /* About 5Hz */
+	B	deadloop_toggle_led
+mpufault_handler:
+	ldr	r0, =1000*1000/4 /* About 2Hz */
+	B	deadloop_toggle_led
+busfault_handler:
+	ldr	r0, =1000*1000/2 /* About 1Hz */
+	B	deadloop_toggle_led
+usagefault_handler:
+	ldr	r0, =1000*1000 /* About 0.5Hz */
+	B	deadloop_toggle_led
+
+/*
+ * GNU seems to have a problem with generating PC relative address using
+ * the ADR command on CM3. As a workaround, the relocation code will have to
+ * do some math to generate the addresses for the information below.
+ */
+
+offsets_rel:
+/*
+ * Needed by board_init_f to identify load/run area
+ */
+.globl _TEXT_BASE
+_TEXT_BASE:
+	.word	CONFIG_SYS_TEXT_BASE
+
+.globl _bss_start_ofs
+_bss_start_ofs:
+	.word __bss_start - _start
+.globl _bss_end_ofs
+_bss_end_ofs:
+	.word __bss_end__ - _start
+.globl _end_ofs
+_end_ofs:
+	.word _end - _start
+
+#ifdef CONFIG_USE_BOARD_MPU_TABLE
+_board_mpu_table_offs:
+	.word board_mpu_table - CONFIG_SYS_TEXT_BASE
+#endif
+/*
+ * These may not be needed
+ */
+/*
+_rel_dyn_start_ofs:
+	.word __rel_dyn_start - CONFIG_SYS_TEXT_BASE
+_rel_dyn_end_ofs:
+	.word __rel_dyn_end - CONFIG_SYS_TEXT_BASE
+_dynsym_start_ofs:
+	.word __dynsym_start - CONFIG_SYS_TEXT_BASE
+*/
+
+/* IRQ stack memory + 8 bytes */
+.globl IRQ_STACK_START_IN
+IRQ_STACK_START_IN:
+	.word	0x0badc0de
+
+/*************************************************************************
+ *
+ * Startup Code (reset vector)
+ *
+ * Call low level CPU/board initialization
+ * Branch (one way) to the board initialization (board_init_f)
+ * Note: stack is initialized as part of M3 reset/boot
+ *
+ *************************************************************************/
+reset:
+
+	mov	r0, pc
+	ldr	r1, =offset_mark
+offset_mark:
+	ldr	r2, =offsets_rel
+	sub	r1, r1, r2
+	sub	r4, r0, r1
+	mov	r9, r4 /* R9 has address to offset_rel */
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+	/* Low level init */
+	bl	cpu_init_crit
+#endif
+
+	/* Relocate data now or hope something doesn't break in all
+	 * the 'relative' code and data elsewhere.
+	 */
+	bl	relocate_pre
+
+/* call board_init_f, absolute jump without return */
+call_board_init_f:
+	ldr	r0, =board_init_f
+	bx	r0
+
+/*************************************************************************
+ *
+ * void relocate_pre(void)
+ *
+ * Early code relocation to RAM - this may not be 'proper'
+ *
+ *************************************************************************/
+relocate_pre:
+	push	{lr}
+
+	mov	r4, r9
+
+	/* Get destination start and end addresses */
+	ldr	r1, [r4, #(_TEXT_BASE - offsets_rel)]
+	ldr	r2, [r4, #(_end_ofs - offsets_rel)]
+	add	r2, r2, r1
+
+	/* Copy everything */
+	ldr	r0, =_start
+pre_copy_loop:
+	cmp	r1, r2
+	beq	pre_copy_loop_exit
+	ldr	r3, [r0]
+	add	r0, r0, #4
+	str	r3, [r1]
+	add	r1, r1, #4
+	B	pre_copy_loop
+
+pre_copy_loop_exit:
+	/* Clear BSS */
+	ldr	r3, [r4, #(_TEXT_BASE - offsets_rel)]
+	ldr	r1, [r4, #(_bss_start_ofs - offsets_rel)]
+	ldr	r2, [r4, #(_bss_end_ofs - offsets_rel)]
+	add	r1, r1, r3
+	add	r2, r2, r3
+	mov	r3, #0
+
+clear_bss:
+	str	r3, [r1]
+	add	r1, r1, #4
+	cmp	r1, r2
+	bne	clear_bss
+
+	pop	{pc}
+
+/*************************************************************************
+ *
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code. Called from board_init_f().
+ *
+ *************************************************************************/
+	.align 3 /* Align for C to assembly call */
+.globl	relocate_code
+relocate_code:
+	/* Setup new stack */
+	mov	sp, r0
+
+/*
+ * We are done. Do not return, instead branch to second part of board
+ * initialization, now running from RAM.
+ */
+jump_2_ram:
+	ldr	r3, =board_init_r
+	/* setup parameters for board_init_r */
+	mov	r0, r1		/* gd_t */
+	mov	r1, r2		/* dest_addr */
+	/* jump to it ... */
+	bx	r3
+
+/*************************************************************************
+ *
+ * CPU_init_critical registers
+ *
+ * Save link register
+ * Call lowlevel_init function for board specific setup
+ *
+ *************************************************************************/
+cpu_init_crit:
+	push	{lr}
+
+	/* Setup MPU */
+#ifdef CONFIG_USE_BOARD_MPU_TABLE
+	mov	r4, r9
+	ldr	r0, [r4, #(_board_mpu_table_offs - offsets_rel)]
+#else
+	mov	r0, #0
+#endif
+	bl	mpu_init
+	mov	r0, #1
+	bl	mpu_enable
+
+	/* Jump to board specific initialization */
+	bl	lpc17_board_init
+
+	pop	{pc}
+
+/*************************************************************************
+ *
+ * deadloop_toggle_led(unsigned rate)
+ *
+ * Called when an error occurs in u-boot. Will toggle an LED
+ *
+ *************************************************************************/
+deadloop_toggle_led:
+	ldr	r2, =CONFIG_SYS_INIT_SP_ADDR
+	mov	sp, r2
+	mov	r4, r0
+deadloop_toggle_led_loop:
+	bl	red_LED_on
+	mov	r0, r4
+	bl	udelay
+	bl	red_LED_off
+	mov	r0, r4
+	bl	udelay
+	B	deadloop_toggle_led_loop
+
diff -Naur u-boot-2011.06/arch/arm/cpu/cortex-m3/u-boot.lds u-boot-2011.06-lpc1788/arch/arm/cpu/cortex-m3/u-boot.lds
--- u-boot-2011.06/arch/arm/cpu/cortex-m3/u-boot.lds	1969-12-31 16:00:00.000000000 -0800
+++ u-boot-2011.06-lpc1788/arch/arm/cpu/cortex-m3/u-boot.lds	2011-07-27 11:35:08.683357878 -0700
@@ -0,0 +1,80 @@
+/*
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	.text	:
+	{
+		arch/arm/cpu/cortex-m3/start.o	(.text)
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data : {
+	}
+
+	. = ALIGN(4);
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+
+	.rel.dyn : {
+		__rel_dyn_start = .;
+		*(.rel*)
+		__rel_dyn_end = .;
+	}
+
+	.dynsym : {
+		__dynsym_start = .;
+		*(.dynsym)
+	}
+
+	. = ALIGN(4);
+	_end = .;
+
+	.bss __rel_dyn_start (OVERLAY) : {
+		__bss_start = .;
+		*(.bss)
+		 . = ALIGN(4);
+		__bss_end__ = .;
+	}
+
+	/DISCARD/ : { *(.dynstr*) }
+	/DISCARD/ : { *(.dynamic*) }
+	/DISCARD/ : { *(.plt*) }
+	/DISCARD/ : { *(.interp*) }
+	/DISCARD/ : { *(.gnu*) }
+}
diff -Naur u-boot-2011.06/arch/arm/include/asm/arch-cortex-m3/cortex-m3.h u-boot-2011.06-lpc1788/arch/arm/include/asm/arch-cortex-m3/cortex-m3.h
--- u-boot-2011.06/arch/arm/include/asm/arch-cortex-m3/cortex-m3.h	1969-12-31 16:00:00.000000000 -0800
+++ u-boot-2011.06-lpc1788/arch/arm/include/asm/arch-cortex-m3/cortex-m3.h	2011-08-16 11:33:57.292856095 -0700
@@ -0,0 +1,74 @@
+#ifndef __CORTEX_M3_H
+#define __CORTEX_M3_H
+
+/*
+ * Copyright (C) 2011 by NXP Semiconductors
+ * All rights reserved.
+ *
+ * @Author: Kevin Wells
+ * @Descr: Cortex M3 common definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#define CM3_AIRCR		0xE000ED0C
+#define CM3_MPU_REGBASE		0xE000ED90
+
+#define CM3_MPU_DIS_INST_FETCHES	(1 << 28)
+#define CM3_MPU_DATA_NO_NO		(0 << 24)
+#define CM3_MPU_DATA_RW_NO		(1 << 24)
+#define CM3_MPU_DATA_RW_RO		(2 << 24)
+#define CM3_MPU_DATA_RW_RW		(3 << 24)
+#define CM3_MPU_DATA_RO_NO		(5 << 24)
+#define CM3_MPU_DATA_RO_RO		(6 << 24)
+#define CM3_MPU_SHARED			(1 << 18)
+#define CM3_MPU_CACHABLE		(1 << 17)
+#define CM3_MPU_BUFFERABLE		(1 << 16)
+#define CM3_MPU_SIZE_32B		(4 << 1)
+#define CM3_MPU_SIZE_64B		(5 << 1)
+#define CM3_MPU_SIZE_128B		(6 << 1)
+#define CM3_MPU_SIZE_256B		(7 << 1)
+#define CM3_MPU_SIZE_512B		(8 << 1)
+#define CM3_MPU_SIZE_1KB		(9 << 1)
+#define CM3_MPU_SIZE_2KB		(10 << 1)
+#define CM3_MPU_SIZE_4KB		(11 << 1)
+#define CM3_MPU_SIZE_8KB		(12 << 1)
+#define CM3_MPU_SIZE_16KB		(13 << 1)
+#define CM3_MPU_SIZE_32KB		(14 << 1)
+#define CM3_MPU_SIZE_64KB		(15 << 1)
+#define CM3_MPU_SIZE_128KB		(16 << 1)
+#define CM3_MPU_SIZE_256KB		(17 << 1)
+#define CM3_MPU_SIZE_512KB		(18 << 1)
+#define CM3_MPU_SIZE_1MB		(19 << 1)
+#define CM3_MPU_SIZE_2MB		(20 << 1)
+#define CM3_MPU_SIZE_4MB		(21 << 1)
+#define CM3_MPU_SIZE_8MB		(22 << 1)
+#define CM3_MPU_SIZE_16MB		(23 << 1)
+#define CM3_MPU_SIZE_32MB		(24 << 1)
+#define CM3_MPU_SIZE_64MB		(25 << 1)
+#define CM3_MPU_SIZE_128MB		(26 << 1)
+#define CM3_MPU_SIZE_256MB		(27 << 1)
+#define CM3_MPU_SIZE_512MB		(28 << 1)
+#define CM3_MPU_SIZE_1GB		(29 << 1)
+#define CM3_MPU_SIZE_2GB		(30 << 1)
+#define CM3_MPU_SIZE_4GB		(31 << 1)
+#define CM3_MPU_ENABLE			(1 << 0)
+
+/* Initialize Cortex M3 MPU */
+void mpu_init(const unsigned long *init_table);
+
+void mpu_enable(int enable);
+
+#endif /* __CORTEX_M3_H */
diff -Naur u-boot-2011.06/arch/arm/include/asm/arch-lpc17xx/hardware.h u-boot-2011.06-lpc1788/arch/arm/include/asm/arch-lpc17xx/hardware.h
--- u-boot-2011.06/arch/arm/include/asm/arch-lpc17xx/hardware.h	1969-12-31 16:00:00.000000000 -0800
+++ u-boot-2011.06-lpc1788/arch/arm/include/asm/arch-lpc17xx/hardware.h	2011-07-22 13:04:30.696705163 -0700
@@ -0,0 +1,32 @@
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+/*
+ * Copyright (C) 2011 by NXP Semiconductors
+ * All rights reserved.
+ *
+ * @Author: Kevin Wells
+ * @Descr: LPC17xx register addresses
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#if defined(CONFIG_LPC17XX)
+#include <asm/arch-lpc17xx/lpc17_regs.h>
+#else
+#error No hardware file defined for this configuration
+#endif
+
+#endif /* __ASM_ARCH_HARDWARE_H */
diff -Naur u-boot-2011.06/arch/arm/include/asm/arch-lpc17xx/lpc17_clock_checks.h u-boot-2011.06-lpc1788/arch/arm/include/asm/arch-lpc17xx/lpc17_clock_checks.h
--- u-boot-2011.06/arch/arm/include/asm/arch-lpc17xx/lpc17_clock_checks.h	1969-12-31 16:00:00.000000000 -0800
+++ u-boot-2011.06-lpc1788/arch/arm/include/asm/arch-lpc17xx/lpc17_clock_checks.h	2011-07-29 13:56:37.493995568 -0700
@@ -0,0 +1,141 @@
+#ifndef __LPC17_CLOCK_CHECKS_H
+#define __LPC17_CLOCK_CHECKS_H
+
+/*
+ * Copyright (C) 2011 by NXP Semiconductors
+ * All rights reserved.
+ *
+ * @Author: Kevin Wells
+ * @Descr: LPC17xx clock definition validation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <config.h>
+
+/*
+ * Compile time sanity checks for defined board clock setup
+ */
+#ifndef CONFIG_LPC17_OSC_RATE
+#error CONFIG_LPC17_OSC_RATE is not setup, set to the external osc rate
+#endif
+#ifndef CONFIG_LPC17_PLL0_USE_EXTOSC
+#error CONFIG_LPC17_PLL0_USE_EXTOSC is not setup, must be 0 or 1
+#endif
+#ifndef CONFIG_LPC17_PLL0_ENABLE
+#error CONFIG_LPC17_PLL0_ENABLE is not setup, must be 0 or 1
+#endif
+#ifndef CONFIG_LPC17_PLL1_ENABLE
+#error CONFIG_LPC17_PLL1_ENABLE is not setup, must be 0 or 1
+#endif
+#ifndef CONFIG_LPC17_PLL0_FOR_CPU
+#error CONFIG_LPC17_PLL0_FOR_CPU is not setup, must be 0 or 1
+#endif
+#ifndef CONFIG_LPC17_CPU_DIV
+#error CONFIG_LPC17_CPU_DIV is not setup, must be between 1 and 31
+#endif
+#ifndef CONFIG_LPC17_USB_DIV
+#error CONFIG_LPC17_USB_DIV is not setup, must be 0, 4, or 6
+#endif
+#ifndef CONFIG_LPC17_EMC_HALFCPU
+#error CONFIG_LPC17_EMC_HALFCPU is not setup, must be 0 or 1
+#endif
+#ifndef CONFIG_LPC17_PCLK_DIV
+#error CONFIG_LPC17_PCLK_DIV is not setup, must be between 1 and 31
+#endif
+#ifndef CONFIG_LPC17_FLASH_CLOCKS
+#error CONFIG_LPC17_FLASH_CLOCKS is not setup, must be between 1 and 6
+#endif
+
+/* PLL0 checks */
+#if CONFIG_LPC17_PLL0_ENABLE==1
+
+#if CONFIG_LPC17_PLL0_USE_EXTOSC==0
+/* PLL0 rate based on internal oscillator */
+#define PLL0TMPRATE (LPC17_INTOSCRATE * CONFIG_LPC17_PLL0_M)
+#else
+/* PLL0 rate based on external oscillator */
+#define PLL0TMPRATE (CONFIG_LPC17_OSC_RATE * CONFIG_LPC17_PLL0_M)
+#endif
+
+#if PLL0TMPRATE < 9750000
+#error PLL0 rate is too low
+#endif
+#if PLL0TMPRATE > 160000000
+#error PLL0 rate is too high
+#endif
+#if (PLL0TMPRATE * 2 * CONFIG_LPC17_PLL0_P) < 156000000
+#error PLL0 FCCO rate is too low
+#endif
+#if (PLL0TMPRATE * 2 * CONFIG_LPC17_PLL0_P) > 320000000
+#error PLL0 FCCO rate is too high
+#endif
+#endif /* CONFIG_LPC17_PLL0_ENABLE==1 */
+
+/* PLL1 checks */
+#if CONFIG_LPC17_PLL1_ENABLE==1
+
+/* PLL1 rate based on external oscillator only */
+#define PLL1TMPRATE (CONFIG_LPC17_OSC_RATE * CONFIG_LPC17_PLL1_M)
+
+#if PLL1TMPRATE < 9750000
+#error PLL1 rate is too low
+#endif
+#if PLL1TMPRATE > 160000000
+#error PLL1 rate is too high
+#endif
+#if (PLL1TMPRATE * 2 * CONFIG_LPC17_PLL1_P) < 156000000
+#error PLL1 FCCO rate is too low
+#endif
+#if (PLL1TMPRATE * 2 * CONFIG_LPC17_PLL1_P) > 320000000
+#error PLL1 FCCO rate is too high
+#endif
+#endif /* CONFIG_LPC17_PLL1_ENABLE==1 */
+
+/* Verify CPU divider */
+#if CONFIG_LPC17_CPU_DIV < 1
+#error CONFIG_LPC17_CPU_DIV is too low, 1 is the minimum
+#endif
+#if CONFIG_LPC17_CPU_DIV > 31
+#error CONFIG_LPC17_CPU_DIV is too high, 31 is the maximum
+#endif
+
+/* Verify USB divider */
+#if CONFIG_LPC17_USB_DIV!= 0
+#if CONFIG_LPC17_USB_DIV!=4
+#if CONFIG_LPC17_USB_DIV!=6
+#error CONFIG_LPC17_USB_DIV must be 0, 4, or 6
+#endif
+#endif
+#endif
+
+/* Verify peripheral divider */
+#if CONFIG_LPC17_PCLK_DIV < 1
+#error CONFIG_LPC17_PCLK_DIV is too low, 1 is the minimum
+#endif
+#if CONFIG_LPC17_PCLK_DIV > 31
+#error CONFIG_LPC17_PCLK_DIV is too high, 31 is the maximum
+#endif
+
+/* Verify FLASH clocks */
+#if CONFIG_LPC17_FLASH_CLOCKS < 1
+#error CONFIG_LPC17_FLASH_CLOCKS is too low, 1 is the minimum
+#endif
+#if CONFIG_LPC17_FLASH_CLOCKS > 6
+#error CONFIG_LPC17_FLASH_CLOCKS is too high, 6 is the maximum
+#endif
+
+#endif /* __LPC17_CLOCK_CHECKS_H */
+
diff -Naur u-boot-2011.06/arch/arm/include/asm/arch-lpc17xx/lpc17_clocks.h u-boot-2011.06-lpc1788/arch/arm/include/asm/arch-lpc17xx/lpc17_clocks.h
--- u-boot-2011.06/arch/arm/include/asm/arch-lpc17xx/lpc17_clocks.h	1969-12-31 16:00:00.000000000 -0800
+++ u-boot-2011.06-lpc1788/arch/arm/include/asm/arch-lpc17xx/lpc17_clocks.h	2011-07-25 16:14:18.433357828 -0700
@@ -0,0 +1,70 @@
+#ifndef __LPC17_CLOCKS_H
+#define __LPC17_CLOCKS_H
+
+/*
+ * Copyright (C) 2011 by NXP Semiconductors
+ * All rights reserved.
+ *
+ * @Author: Kevin Wells
+ * @Descr: LPC17xx clock control
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+typedef enum {
+	LPC17_CLK_LCD = 0,
+	LPC17_CLK_TIM0,
+	LPC17_CLK_TIM1,
+	LPC17_CLK_UART0,
+	LPC17_CLK_UART1,
+	LPC17_CLK_PWM0,
+	LPC17_CLK_PWM1,
+	LPC17_CLK_I2C0,
+	LPC17_CLK_UART4,
+	LPC17_CLK_RTC,
+	LPC17_CLK_SSP1,
+	LPC17_CLK_EMC,
+	LPC17_CLK_ADC,
+	LPC17_CLK_CAN1,
+	LPC17_CLK_CAN2,
+	LPC17_CLK_GPIO,
+	LPC17_CLK_RESERVED,
+	LPC17_CLK_MCPWM,
+	LPC17_CLK_QEI,
+	LPC17_CLK_I2C1,
+	LPC17_CLK_SSP2,
+	LPC17_CLK_SSP0,
+	LPC17_CLK_TIM2,
+	LPC17_CLK_TIM3,
+	LPC17_CLK_UART2,
+	LPC17_CLK_UART3,
+	LPC17_CLK_I2C2,
+	LPC17_CLK_I2S,
+	LPC17_CLK_SDC,
+	LPC17_CLK_DMA,
+	LPC17_CLK_ENET,
+	LPC17_CLK_USB
+} lpc17xx_clk;
+
+extern unsigned long lpc17_get_pll0_rate(void);
+extern unsigned long lpc17_get_pll1_rate(void);
+extern unsigned long lpc17_get_cpu_rate(void);
+extern unsigned long lpc17_get_usb_rate(void);
+extern unsigned long lpc17_get_emc_rate(void);
+extern unsigned long lpc17_get_pclk_rate(void);
+extern void lpc17_clk_enable(lpc17xx_clk, int enable);
+extern void lpc17_setup_clocks(void);
+
+#endif /* __LPC17_CLOCKS_H */
diff -Naur u-boot-2011.06/arch/arm/include/asm/arch-lpc17xx/lpc17_gpio.h u-boot-2011.06-lpc1788/arch/arm/include/asm/arch-lpc17xx/lpc17_gpio.h
--- u-boot-2011.06/arch/arm/include/asm/arch-lpc17xx/lpc17_gpio.h	1969-12-31 16:00:00.000000000 -0800
+++ u-boot-2011.06-lpc1788/arch/arm/include/asm/arch-lpc17xx/lpc17_gpio.h	2011-08-12 16:39:45.130124698 -0700
@@ -0,0 +1,39 @@
+#ifndef __LPC17_GPIO_H
+#define __LPC17_GPIO_H
+
+/*
+ * Copyright (C) 2011 by NXP Semiconductors
+ * All rights reserved.
+ *
+ * @Author: Kevin Wells
+ * @Descr: LPC17xx GPIO functions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+/* Set a GPIO as an input */
+void lpc17xx_gpio_set_input(unsigned char grp, unsigned char pin);
+
+/* Set a GPIO as an output */
+void lpc17xx_gpio_set_output(unsigned char grp,unsigned char pin);
+
+/* Set a output GPIO to a specific state */
+void lpc17xx_gpio_set_state(unsigned char grp, unsigned char pin, int st);
+
+/* Return the state of an input GPIO */
+int lpc17xx_gpio_get_state(unsigned char grp, unsigned char pin);
+
+#endif /* __LPC17_GPIO_H */
+
diff -Naur u-boot-2011.06/arch/arm/include/asm/arch-lpc17xx/lpc17_iaplib.h u-boot-2011.06-lpc1788/arch/arm/include/asm/arch-lpc17xx/lpc17_iaplib.h
--- u-boot-2011.06/arch/arm/include/asm/arch-lpc17xx/lpc17_iaplib.h	1969-12-31 16:00:00.000000000 -0800
+++ u-boot-2011.06-lpc1788/arch/arm/include/asm/arch-lpc17xx/lpc17_iaplib.h	2011-08-15 11:21:50.291373853 -0700
@@ -0,0 +1,92 @@
+#ifndef __LPC17_IAPLIB_H
+#define __LPC17_IAPLIB_H
+
+/*
+ * Copyright (C) 2011 by NXP Semiconductors
+ * All rights reserved.
+ *
+ * @Author: Kevin Wells
+ * @Descr: LPC17xx FLASH IAP interface library
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+/* IAP statuses */
+typedef enum {
+	iap_cmd_success = 0,
+	iap_invalid_command,
+	iap_src_addr_error,
+	iap_dst_addr_error,
+	iap_src_addr_not_mapped,
+	iap_dst_addr_not_mapped,
+	iap_count_error,
+	iap_invalid_sector,
+	iap_sector_not_blank,
+	iap_sector_not_prepared,
+	iap_compare_error,
+	iap_busy
+} lpc17_iap_status;
+
+typedef struct {
+	unsigned long offset;
+	unsigned long size;
+} lpc17_iap_block_list;
+
+/* Return the number of sectors */
+unsigned long lpc17_iap_get_sectors(void);
+
+/* Return the FLASH size */
+unsigned long lpc17_iap_get_size(void);
+
+/* Return a list of block addresses and sizes */
+const lpc17_iap_block_list *lpc17_iap_get_block_list(void);
+
+/* Prepare sectors for erase or write */
+lpc17_iap_status lpc17_iap_prepare_sectors(unsigned long start,
+	unsigned long end);
+
+/* Copy RAM to FLASH */
+lpc17_iap_status lpc17_iap_ram_to_flash(unsigned long dst,
+	unsigned long src, unsigned long bytes);
+
+/* Erase sectors */
+lpc17_iap_status lpc17_iap_erase_sectors(unsigned long start,
+	unsigned long end);
+
+/* Blank check sectors */
+lpc17_iap_status lpc17_iap_blank_check_sectors(unsigned long start,
+	unsigned long end, unsigned long *bad_addr, unsigned long *bad_data);
+
+/* Read part identification number */
+unsigned long lpc17_iap_read_part_id_num(void);
+
+/* Read boot code version */
+unsigned long lpc17_iap_read_boot_code_version(void);
+
+/* Read device serial number */
+void lpc17_iap_read_serial_num(unsigned long sn[4]);
+
+/* Compare data */
+lpc17_iap_status lpc17_iap_compare(unsigned long dst, unsigned long src,
+	unsigned long bytes, unsigned long *mis_addr);
+
+/* Re-invoke ISP */
+void lpc17_iap_reinvoke_isp(void);
+
+/* Initialize IAP library - call this first */
+void lpc17_iap_init(unsigned clkrate);
+
+#endif /* __LPC17_IAPLIB_H */
+
diff -Naur u-boot-2011.06/arch/arm/include/asm/arch-lpc17xx/lpc17_iocon.h u-boot-2011.06-lpc1788/arch/arm/include/asm/arch-lpc17xx/lpc17_iocon.h
--- u-boot-2011.06/arch/arm/include/asm/arch-lpc17xx/lpc17_iocon.h	1969-12-31 16:00:00.000000000 -0800
+++ u-boot-2011.06-lpc1788/arch/arm/include/asm/arch-lpc17xx/lpc17_iocon.h	2011-07-27 09:11:07.393420150 -0700
@@ -0,0 +1,114 @@
+#ifndef __LPC17_IOCON_H
+#define __LPC17_IOCON_H
+
+/*
+ * Copyright (C) 2011 by NXP Semiconductors
+ * All rights reserved.
+ *
+ * @Author: Kevin Wells
+ * @Descr: LPC17xx IOCON setup support functions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+/* Function mode for pins */
+typedef enum {
+	LPC17_NO_PULLUP	= 0,
+	LPC17_PULLDOWN	= 1,
+	LPC17_PULLUP	= 2,
+	LPC17_REPEATER	= 3
+} lpc17_mode;
+
+/*
+ * Structure for setting up IOCON type D pins. See the User manual for setup.
+ */
+typedef struct {
+	u16 func	: 3;
+	u16 mode	: 2;
+	u16 hys		: 1; /* true to enable hysteresis */
+	u16 inv		: 1; /* true to invert signal */
+	u16 slew	: 1; /* true to enable fast slew */
+	u16 od		: 1; /* true to enable simulated open drain */
+} lpc17_iocon_d_setup;
+
+/*
+ * Structure for setting up IOCON type A pins. See the User manual for setup.
+ */
+typedef struct {
+	u16 func	: 3;
+	u16 mode	: 2;
+	u16 hys		: 1; /* true to enable hysteresis */
+	u16 inv		: 1; /* true to invert signal */
+	u16 admode	: 1; /* true for digital, false for analog */
+	u16 filter	: 1; /* true to disable glitch filter */
+	u16 od		: 1; /* true to enable simulated open drain */
+	u16 dacen	: 1; /* true to enable DAC */
+} lpc17_iocon_a_setup;
+
+/*
+ * Structure for setting up IOCON type U pins. See the User manual for setup.
+ */
+typedef struct {
+	u16 func	: 3;
+} lpc17_iocon_u_setup;
+
+/*
+ * Structure for setting up IOCON type I pins. See the User manual for setup.
+ */
+typedef struct {
+	u16 func	: 3;
+	u16 inv		: 1; /* true to invert signal */
+	u16 hs		: 1; /* true to disable glitch filter */
+	u16 hidrive	: 1; /* true to enable 20mA sink */
+} lpc17_iocon_i_setup;
+
+/*
+ * Structure for setting up IOCON type W pins. See the User manual for setup.
+ */
+typedef struct {
+	u16 func	: 3;
+	u16 mode	: 2;
+	u16 hys		: 1; /* true to enable hysteresis */
+	u16 inv		: 1; /* true to invert signal */
+	u16 filter	: 1; /* true to disable glitch filter */
+	u16 slew	: 1; /* true to enable fast slew */
+	u16 od		: 1; /* true to enable simulated open drain */
+} lpc17_iocon_w_setup;
+
+typedef enum {
+	IOCON_D_TYPE = 0,
+	IOCON_A_TYPE,
+	IOCON_U_TYPE,
+	IOCON_I_TYPE,
+	IOCON_W_TYPE
+} LPC17_IOCON_TYPE;
+
+typedef struct {
+	u16 grp		: 3;
+	u16 pin		: 5;
+	u16 iocon_type	: 3;
+	union {
+		lpc17_iocon_d_setup d;
+		lpc17_iocon_a_setup a;
+		lpc17_iocon_u_setup u;
+		lpc17_iocon_i_setup i;
+		lpc17_iocon_w_setup w;
+	} iocon;
+} iocon_pin_type;
+
+/* Set the configuration of a IOCON pin */
+void lpc17_iocon_setup(iocon_pin_type *iocon_pin);
+
+#endif /* __LPC17_IOCON_H */
diff -Naur u-boot-2011.06/arch/arm/include/asm/arch-lpc17xx/lpc17_mac.h u-boot-2011.06-lpc1788/arch/arm/include/asm/arch-lpc17xx/lpc17_mac.h
--- u-boot-2011.06/arch/arm/include/asm/arch-lpc17xx/lpc17_mac.h	1969-12-31 16:00:00.000000000 -0800
+++ u-boot-2011.06-lpc1788/arch/arm/include/asm/arch-lpc17xx/lpc17_mac.h	2011-08-15 16:00:20.762174927 -0700
@@ -0,0 +1,76 @@
+#ifndef __LPC17_MAC_H
+#define __LPC17_MAC_H
+
+/*
+ * Copyright (C) 2011 by NXP Semiconductors
+ * All rights reserved.
+ *
+ * @Author: Kevin Wells
+ * @Descr: LPC17xx MAC (ethernet) support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+/*
+ * MAC block registers
+ */
+#define MAC_MAC1		LPC17_ENET(0x000)
+#define MAC_MAC2		LPC17_ENET(0x004)
+#define MAC_IPGT		LPC17_ENET(0x008)
+#define MAC_IPGR		LPC17_ENET(0x00C)
+#define MAC_CLRT		LPC17_ENET(0x010)
+#define MAC_MAXF		LPC17_ENET(0x014)
+#define MAC_SUPP		LPC17_ENET(0x018)
+#define MAC_TEST		LPC17_ENET(0x01C)
+#define MAC_MCFG		LPC17_ENET(0x020)
+#define MAC_MCMD		LPC17_ENET(0x024)
+#define MAC_MADR		LPC17_ENET(0x028)
+#define MAC_MWTD		LPC17_ENET(0x02C)
+#define MAC_MRDD		LPC17_ENET(0x030)
+#define MAC_MIND		LPC17_ENET(0x034)
+#define MAC_SA0			LPC17_ENET(0x040)
+#define MAC_SA1			LPC17_ENET(0x044)
+#define MAC_SA2			LPC17_ENET(0x048)
+#define MAC_COMMAND		LPC17_ENET(0x100)
+#define MAC_STATUS		LPC17_ENET(0x104)
+#define MAC_RXDESC		LPC17_ENET(0x108)
+#define MAC_RXSTATUS		LPC17_ENET(0x10C)
+#define MAC_RXDESCNUM		LPC17_ENET(0x110)
+#define MAC_RXPRODIDX		LPC17_ENET(0x114)
+#define MAC_RXCONSIDX		LPC17_ENET(0x118)
+#define MAC_TXDESC		LPC17_ENET(0x11C)
+#define MAC_TXSTATUS		LPC17_ENET(0x120)
+#define MAC_TXDESCNUM		LPC17_ENET(0x124)
+#define MAC_TXPRODIDX		LPC17_ENET(0x128)
+#define MAC_TXCONSIDX		LPC17_ENET(0x12C)
+#define MAC_TSV0		LPC17_ENET(0x158)
+#define MAC_TSV1		LPC17_ENET(0x15C)
+#define MAC_RSV			LPC17_ENET(0x160)
+#define MAC_FLOWCTRLCNTR	LPC17_ENET(0x170)
+#define MAC_FLOWCTRLSTS		LPC17_ENET(0x174)
+#define MAC_RXFILTCTRL		LPC17_ENET(0x200)
+#define MAC_RXFILTWOLSTS	LPC17_ENET(0x204)
+#define MAC_TXFILTWOLCLR	LPC17_ENET(0x208)
+#define MAC_HASHFLTRL		LPC17_ENET(0x210)
+#define MAC_HASHFLTRH		LPC17_ENET(0x214)
+#define MAC_INTSTAT		LPC17_ENET(0xFE0)
+#define MAC_INTENAB		LPC17_ENET(0xFE4)
+#define MAC_INTCLR		LPC17_ENET(0xFE8)
+#define MAC_INTSET		LPC17_ENET(0xFEC)
+#define MAC_POWERDOWN		LPC17_ENET(0xFF4)
+#define MAC_MODULEID		LPC17_ENET(0xFFC)
+
+#endif /* __LPC17_MAC_H */
+
diff -Naur u-boot-2011.06/arch/arm/include/asm/arch-lpc17xx/lpc17_regs.h u-boot-2011.06-lpc1788/arch/arm/include/asm/arch-lpc17xx/lpc17_regs.h
--- u-boot-2011.06/arch/arm/include/asm/arch-lpc17xx/lpc17_regs.h	1969-12-31 16:00:00.000000000 -0800
+++ u-boot-2011.06-lpc1788/arch/arm/include/asm/arch-lpc17xx/lpc17_regs.h	2011-07-27 15:36:03.093357907 -0700
@@ -0,0 +1,221 @@
+#ifndef __LPC17XX_REGS_H
+#define __LPC17XX_REGS_H
+
+/*
+ * Copyright (C) 2011 by NXP Semiconductors
+ * All rights reserved.
+ *
+ * @Author: Kevin Wells
+ * @Descr: LPC17xx register addresses
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <config.h>
+
+/*
+ * LPC17xx regions
+ */
+#define LPC17_FLASH_BASE		0x00000000
+#define LPC17_SRAM1_BASE		0x10000000
+#define LPC17_BOOTROM_BASE		0x1FFF0000
+#define LPC17_SRAM2_BASE		0x20000000
+#define LPC17_AHB_BASE			0x20080000
+#define LPC17_APB_BASE			0x40000000
+#define LPC17_EMC_STATIC0		0x80000000
+#define LPC17_EMC_STATIC1		0x90000000
+#define LPC17_EMC_STATIC2		0x98000000
+#define LPC17_EMC_STATIC3		0x9C000000
+#define LPC17_EMC_DRAM0			0xA0000000
+#define LPC17_EMC_DRAM1			0xB0000000
+#define LPC17_EMC_DRAM2			0xC0000000
+#define LPC17_EMC_DRAM3			0xD0000000
+#define LPC17_M3_PRVBUS			0xE0000000
+
+/*
+ * APB peripheral register bases
+ */
+#define LPC17_WDT(x)			(LPC17_APB_BASE + 0x00000000 + (x))
+#define LPC17_TIMER0			(LPC17_APB_BASE + 0x00004000)
+#define LPC17_TIMER1			(LPC17_APB_BASE + 0x00008000)
+#define LPC17_UART0			(LPC17_APB_BASE + 0x0000C000)
+#define LPC17_UART1			(LPC17_APB_BASE + 0x00010000)
+#define LPC17_PWM0(x)			(LPC17_APB_BASE + 0x00014000 + (x))
+#define LPC17_PWM1(x)			(LPC17_APB_BASE + 0x00018000 + (x))
+#define LPC17_I2C0(x)			(LPC17_APB_BASE + 0x0001C000 + (x))
+#define LPC17_RTC(x)			(LPC17_APB_BASE + 0x00020000 + (x))
+#define LPC17_GPIOINTS(x)		(LPC17_APB_BASE + 0x00028000 + (x))
+#define LPC17_PINCON(x)			(LPC17_APB_BASE + 0x0002C000 + (x))
+#define LPC17_SSP1(x)			(LPC17_APB_BASE + 0x00030000 + (x))
+#define LPC17_ADC(x)			(LPC17_APB_BASE + 0x00034000 + (x))
+#define LPC17_CANRAM(x)			(LPC17_APB_BASE + 0x00038000 + (x))
+#define LPC17_CANREGS(x)		(LPC17_APB_BASE + 0x0003C000 + (x))
+#define LPC17_CANCMN(x)			(LPC17_APB_BASE + 0x00040000 + (x))
+#define LPC17_CAN1(x)			(LPC17_APB_BASE + 0x00044000 + (x))
+#define LPC17_CAN2(x)			(LPC17_APB_BASE + 0x00048000 + (x))
+#define LPC17_I2C1(x)			(LPC17_APB_BASE + 0x0005C000 + (x))
+#define LPC17_SSP0(x)			(LPC17_APB_BASE + 0x00088000 + (x))
+#define LPC17_DAC(x)			(LPC17_APB_BASE + 0x0008C000 + (x))
+#define LPC17_TIMER2			(LPC17_APB_BASE + 0x00090000)
+#define LPC17_TIMER3			(LPC17_APB_BASE + 0x00094000)
+#define LPC17_UART2			(LPC17_APB_BASE + 0x00098000)
+#define LPC17_UART3			(LPC17_APB_BASE + 0x0009C000)
+#define LPC17_I2C2(x)			(LPC17_APB_BASE + 0x000A0000 + (x))
+#define LPC17_UART4			(LPC17_APB_BASE + 0x000A4000)
+#define LPC17_I2S(x)			(LPC17_APB_BASE + 0x000A8000 + (x))
+#define LPC17_SSP2(x)			(LPC17_APB_BASE + 0x000AC000 + (x))
+#define LPC17_MOTORCTL(x)		(LPC17_APB_BASE + 0x000B8000 + (x))
+#define LPC17_QEI(x)			(LPC17_APB_BASE + 0x000BC000 + (x))
+#define LPC17_SDCARD(x)			(LPC17_APB_BASE + 0x000C0000 + (x))
+#define LPC17_SYSCONT(x)		(LPC17_APB_BASE + 0x000FC000 + (x))
+
+/*
+ * AHB peripheral register bases
+ */
+#define LPC17_DMA(x)			(LPC17_AHB_BASE + 0x00000000 + (x))
+#define LPC17_ENET(x)			(LPC17_AHB_BASE + 0x00004000 + (x))
+#define LPC17_LCD(x)			(LPC17_AHB_BASE + 0x00008000 + (x))
+#define LPC17_USB(x)			(LPC17_AHB_BASE + 0x0000C000 + (x))
+#define LPC17_CRC(x)			(LPC17_AHB_BASE + 0x00010000 + (x))
+#define LPC17_GPIO(x)			(LPC17_AHB_BASE + 0x00018000 + (x))
+#define LPC17_EMCREGS(x)		(LPC17_AHB_BASE + 0x0001C000 + (x))
+
+/*
+ * System and clock control registers
+ */
+#define LPC17_SC_FLASHCFG		LPC17_SYSCONT(0x000)
+#define LPC17_SC_PLL0CON		LPC17_SYSCONT(0x080)
+#define LPC17_SC_PLL0CFG		LPC17_SYSCONT(0x084)
+#define LPC17_SC_PLL0STAT		LPC17_SYSCONT(0x088)
+#define LPC17_SC_PLL0FEED		LPC17_SYSCONT(0x08C)
+#define LPC17_SC_PLL1CON		LPC17_SYSCONT(0x0A0)
+#define LPC17_SC_PLL1CFG		LPC17_SYSCONT(0x0A4)
+#define LPC17_SC_PLL1STAT		LPC17_SYSCONT(0x0A8)
+#define LPC17_SC_PLL1FEED		LPC17_SYSCONT(0x0AC)
+#define LPC17_SC_PCON			LPC17_SYSCONT(0x0C0)
+#define LPC17_SC_PCONP			LPC17_SYSCONT(0x0C4)
+#define LPC17_SC_EMCCLKSEL		LPC17_SYSCONT(0x100)
+#define LPC17_SC_CCLKSEL		LPC17_SYSCONT(0x104)
+#define LPC17_SC_USBCLKSEL		LPC17_SYSCONT(0x108)
+#define LPC17_SC_CLKSRCSEL		LPC17_SYSCONT(0x10C)
+#define LPC17_SC_EXTINT			LPC17_SYSCONT(0x140)
+#define LPC17_SC_EXTMODE		LPC17_SYSCONT(0x148)
+#define LPC17_SC_EXTPOLAR		LPC17_SYSCONT(0x14C)
+#define LPC17_SC_RSID			LPC17_SYSCONT(0x180)
+#define LPC17_SC_SCS			LPC17_SYSCONT(0x1A0)
+#define LPC17_SC_PCLKSEL		LPC17_SYSCONT(0x1A8)
+#define LPC17_SC_CLKOUTCFG		LPC17_SYSCONT(0x1C8)
+#define LPC17_SC_RSTCON0		LPC17_SYSCONT(0x1CC)
+#define LPC17_SC_RSTCON1		LPC17_SYSCONT(0x1D0)
+#define LPC17_SC_EMCDLYCTL		LPC17_SYSCONT(0x1DC)
+#define LPC17_SC_EMCCAL			LPC17_SYSCONT(0x1E0)
+
+/*
+ * IOCON registers
+ */
+#define __GRPPIN2OFS(grp, pin)		(((grp) * 128) + ((pin) * 4))
+#define LPC17_IOCON(grp, pin)		LPC17_PINCON(__GRPPIN2OFS(grp, pin))
+
+/*
+ * Fast GPIO registers
+ */
+#define LPC17_FIODIR(grp)		LPC17_GPIO((0x00 + (grp) * 0x20))
+#define LPC17_FIOMASK(grp)		LPC17_GPIO((0x10 + (grp) * 0x20))
+#define LPC17_FIOPIN(grp)		LPC17_GPIO((0x14 + (grp) * 0x20))
+#define LPC17_FIOSET(grp)		LPC17_GPIO((0x18 + (grp) * 0x20))
+#define LPC17_FIOCLR(grp)		LPC17_GPIO((0x1C + (grp) * 0x20))
+
+/*
+ * EMC registers
+ */
+#define LPC17_EMCCTRL			LPC17_EMCREGS(0x000)
+#define LPC17_EMCSTS			LPC17_EMCREGS(0x004)
+#define LPC17_EMCCFG			LPC17_EMCREGS(0x008)
+#define LPC17_EMCDYCTRL			LPC17_EMCREGS(0x020)
+#define LPC17_EMCDYRFSH			LPC17_EMCREGS(0x024)
+#define LPC17_EMCDYRDCFG		LPC17_EMCREGS(0x028)
+#define LPC17_EMCDYTRP			LPC17_EMCREGS(0x030)
+#define LPC17_EMCDYRAS			LPC17_EMCREGS(0x034)
+#define LPC17_EMCDYSREX			LPC17_EMCREGS(0x038)
+#define LPC17_EMCDYAPR			LPC17_EMCREGS(0x03C)
+#define LPC17_EMCDYDAL			LPC17_EMCREGS(0x040)
+#define LPC17_EMCDYWR			LPC17_EMCREGS(0x044)
+#define LPC17_EMCDYRC			LPC17_EMCREGS(0x048)
+#define LPC17_EMCDYRFC			LPC17_EMCREGS(0x04C)
+#define LPC17_EMCDYXSR			LPC17_EMCREGS(0x050)
+#define LPC17_EMCDYRRD			LPC17_EMCREGS(0x054)
+#define LPC17_EMCDYMRD			LPC17_EMCREGS(0x058)
+#define LPC17_EMCEXWAIT			LPC17_EMCREGS(0x080)
+#define LPC17_EMCDDYCFG(x)		LPC17_EMCREGS(0x100 + ((x) * 0x20))
+#define LPC17_EMCDYRASCAS(x)		LPC17_EMCREGS(0x104 + ((x) * 0x20))
+#define LPC17_EMCSTCFG(x)		LPC17_EMCREGS(0x200 + ((x) * 0x20))
+#define LPC17_EMCSTWWEN(x)		LPC17_EMCREGS(0x204 + ((x) * 0x20))
+#define LPC17_EMCSTWOEN(x)		LPC17_EMCREGS(0x208 + ((x) * 0x20))
+#define LPC17_EMCSTWRD(x)		LPC17_EMCREGS(0x20C + ((x) * 0x20))
+#define LPC17_EMCSTWPAGE(x)		LPC17_EMCREGS(0x210 + ((x) * 0x20))
+#define LPC17_EMCSTWWR(x)		LPC17_EMCREGS(0x214 + ((x) * 0x20))
+#define LPC17_EMCSTWTURN(x)		LPC17_EMCREGS(0x218 + ((x) * 0x20))
+
+/*
+ * Timer block registers
+ */
+#define LPC17_TIMER_IR(x)		((x) + 0x00)
+#define LPC17_TIMER_TCR(x)		((x) + 0x04)
+#define LPC17_TIMER_TC(x)		((x) + 0x08)
+#define LPC17_TIMER_PR(x)		((x) + 0x0C)
+#define LPC17_TIMER_PC(x)		((x) + 0x10)
+#define LPC17_TIMER_MCR(x)		((x) + 0x14)
+#define LPC17_TIMER_MR0(x)		((x) + 0x18)
+#define LPC17_TIMER_MR1(x)		((x) + 0x1C)
+#define LPC17_TIMER_MR2(x)		((x) + 0x20)
+#define LPC17_TIMER_MR3(x)		((x) + 0x24)
+#define LPC17_TIMER_CCR(x)		((x) + 0x28)
+#define LPC17_TIMER_CR0(x)		((x) + 0x2C)
+#define LPC17_TIMER_CR1(x)		((x) + 0x30)
+#define LPC17_TIMER_EMR(x)		((x) + 0x3C)
+#define LPC17_TIMER_CTCR(x)		((x) + 0x70)
+
+/*
+ * UART block registers
+ */
+#define LPC17_UART_FIFO_DLL(x)		((x) + 0x00)
+#define LPC17_UART_IER_DLM(x)		((x) + 0x04)
+#define LPC17_UART_FCR_IIR(x)		((x) + 0x08)
+#define LPC17_UART_LCR(x)		((x) + 0x0C)
+#define LPC17_UART_MCR(x)		((x) + 0x10)
+#define LPC17_UART_LSR(x)		((x) + 0x14)
+#define LPC17_UART_MSR(x)		((x) + 0x18)
+#define LPC17_UART_SCR(x)		((x) + 0x2C)
+#define LPC17_UART_ACR(x)		((x) + 0x20)
+#define LPC17_UART_FDI(x)		((x) + 0x28)
+#define LPC17_UART_TER(x)		((x) + 0x30)
+
+
+
+
+/*
+ * LPC17xx internal and set RTC oscillator rate
+*/
+#define LPC17_INTOSCRATE		12000000
+#define LPC17_RTCOSCRATE		32000
+#define LPC17_WDTOSCRATE		500000
+
+/*
+ * CPU options
+ */
+#define LPC17_IRAM_SIZE			(64 * 1024)
+
+
+#endif /* _LPC17XX_REGISTERS_H */
diff -Naur u-boot-2011.06/arch/arm/lib/board.c u-boot-2011.06-lpc1788/arch/arm/lib/board.c
--- u-boot-2011.06/arch/arm/lib/board.c	2011-06-27 13:22:42.000000000 -0700
+++ u-boot-2011.06-lpc1788/arch/arm/lib/board.c	2011-08-15 12:15:35.280124176 -0700
@@ -279,7 +279,8 @@
 
 	memset ((void*)gd, 0, sizeof (gd_t));
 
-	gd->mon_len = _bss_end_ofs;
+//	gd->mon_len = _bss_end_ofs; // NXP Workaround for relocation
+	gd->mon_len = 0x80000; // Matches load address for u-boot
 
 	for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
 		if ((*init_fnc_ptr)() != 0) {
diff -Naur u-boot-2011.06/board/nxp/ea1788/config.mk u-boot-2011.06-lpc1788/board/nxp/ea1788/config.mk
--- u-boot-2011.06/board/nxp/ea1788/config.mk	1969-12-31 16:00:00.000000000 -0800
+++ u-boot-2011.06-lpc1788/board/nxp/ea1788/config.mk	2011-08-15 11:55:00.650156256 -0700
@@ -0,0 +1,29 @@
+#
+# (C) Copyright 2000
+# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+# Marius Groeger <mgroeger@sysgo.de>
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#address where u-boot will be relocated
+CONFIG_SYS_TEXT_BASE = 0xA1F80000
diff -Naur u-boot-2011.06/board/nxp/ea1788/ea1788.c u-boot-2011.06-lpc1788/board/nxp/ea1788/ea1788.c
--- u-boot-2011.06/board/nxp/ea1788/ea1788.c	1969-12-31 16:00:00.000000000 -0800
+++ u-boot-2011.06-lpc1788/board/nxp/ea1788/ea1788.c	2011-08-16 16:47:16.640123411 -0700
@@ -0,0 +1,140 @@
+/*
+ * Copyright (C) 2011 by NXP Semiconductors
+ * All rights reserved.
+ *
+ * @Author: Kevin Wells
+ * @Descr: EA1788 board specific setup for u-boot
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/lpc17_regs.h>
+#include <asm/arch/lpc17_clocks.h>
+#include <asm/arch/lpc17_gpio.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void ea1788_setup_pins(void);
+extern void ea1788_mem_if(void);
+
+extern void cm3_reset_cpu(ulong addr);
+#if 0
+/*
+ * Reset command causes a crash on unmodified u-boot code, use
+ * cm_reset instead.
+ */
+void reset_cpu(ulong addr)
+{
+	cm3_reset_cpu(0x0);
+
+}
+#else
+void reset_cpu(ulong addr)
+{
+	cm3_reset_cpu(0x0);
+}
+
+int cm_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	puts ("resetting ...\n");
+
+	udelay (50000);				/* wait 50 ms */
+
+	disable_interrupts();
+	cm3_reset_cpu(0x0);
+
+	/*NOTREACHED*/
+	return 0;
+}
+
+U_BOOT_CMD(
+	cmreset, 1, 0,	cm_reset,
+	"Perform RESET of the CPU",
+	""
+);
+#endif
+
+void red_LED_on(void)
+{
+	lpc17xx_gpio_set_output(2, 26);
+	lpc17xx_gpio_set_state(2, 26, 0);
+}
+
+void red_LED_off(void)
+{
+	lpc17xx_gpio_set_output(2, 26);
+	lpc17xx_gpio_set_state(2, 26, 1);
+}
+
+void lpc17_board_init(void)
+{
+	/* Board specific pin setup */
+	ea1788_setup_pins();
+
+	/* Setup system clocking (CPU setup from CONFIG_ values) */
+	lpc17_setup_clocks();
+
+	/* Board specific setup memory */
+	ea1788_mem_if();
+}
+
+int board_init(void)
+{
+	gd->bd->bi_arch_number = CONFIG_LPC17XX_MACHID;
+
+	/* location of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+
+	return (0);
+}
+
+/*
+ * Test program for LED only
+ */
+int cmd_led(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	if (strcmp (argv[1], "on") == 0) {
+		red_LED_on();
+	} else if (strcmp (argv[1], "off") == 0) {
+		red_LED_off();
+	} else {
+		printf ("Usage:\nled on/off\n");
+		return 1;
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	led ,	2,	1,	cmd_led,
+	"switch status LED on or off",
+	"on/off"
+);
+
diff -Naur u-boot-2011.06/board/nxp/ea1788/Makefile u-boot-2011.06-lpc1788/board/nxp/ea1788/Makefile
--- u-boot-2011.06/board/nxp/ea1788/Makefile	1969-12-31 16:00:00.000000000 -0800
+++ u-boot-2011.06-lpc1788/board/nxp/ea1788/Makefile	2011-08-16 09:42:18.540124133 -0700
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= ea1788.o mem.o net.o nand.o pins.o mpu_setup.o
+SOBJS	:= 
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+OBJS	+= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff -Naur u-boot-2011.06/board/nxp/ea1788/mem.c u-boot-2011.06-lpc1788/board/nxp/ea1788/mem.c
--- u-boot-2011.06/board/nxp/ea1788/mem.c	1969-12-31 16:00:00.000000000 -0800
+++ u-boot-2011.06-lpc1788/board/nxp/ea1788/mem.c	2011-08-15 12:07:05.601064126 -0700
@@ -0,0 +1,137 @@
+/*
+ * Copyright (C) 2011 by NXP Semiconductors
+ * All rights reserved.
+ *
+ * @Author: Kevin Wells
+ * @Descr: EA1788 board specific memory interface setup
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/lpc17_regs.h>
+#include <asm/arch/lpc17_clocks.h>
+
+#define msdelay(x) udelay(x * 1000)
+
+/*
+ * DRAM initialization procedure re-used from the NXP LPC177x_178x
+ * CMSIS software package.
+ *
+ * 32-bit DRAM configuration
+ *
+ * IS42S32800D 8Mx32 256Mbit (32MByte device)
+ * -7BL part
+ * CAS2 <=100MHz, CAS3 > 100MHz
+ * 4096 refresh cycles per 16mS
+ * 12 rows, 9 cols, 4 banks
+ *
+ * Based on timing values below from the u-boot config file (ea1788.h)
+ * CONFIG_LPC17_OSC_RATE	12000000
+ * CONFIG_LPC17_PLL0_USE_EXTOSC	1
+ * CONFIG_LPC17_PLL0_ENABLE	1
+ * CONFIG_LPC17_PLL0_M		9
+ * CONFIG_LPC17_PLL0_P		1
+ * CONFIG_LPC17_PLL1_ENABLE	1
+ * CONFIG_LPC17_PLL1_M		4
+ * CONFIG_LPC17_PLL1_P		2
+ * CONFIG_LPC17_PLL0_FOR_CPU	1
+ * CONFIG_LPC17_CPU_DIV		1
+ * CONFIG_LPC17_USB_DIV		4
+ * CONFIG_LPC17_EMC_HALFCPU	1
+ * CONFIG_LPC17_PCLK_DIV	2
+ *
+ * CPU clock = 108MHz
+ * Bus clock = 54MHz
+ * USB clock = 48MHz
+ * Peripheral clock = 52MHz
+ */
+
+void ea1788_mem_if(void)
+{
+	volatile long tmp32;
+
+	/* Enable clock for EMC */
+	lpc17_clk_enable(LPC17_CLK_ADC, 1);	
+
+	/* Clock delay */
+	__raw_writel(0x1010, LPC17_SC_EMCDLYCTL);
+
+	/* Little endian mode */
+	__raw_writel(0x1, LPC17_EMCCTRL);
+	__raw_writel(0x0, LPC17_EMCCFG);
+
+	/* 4 banks, 12 rows, 9 cols, 8Mx32 */
+	__raw_writel(0x00004480, LPC17_EMCDDYCFG(0));
+
+	/* Timing for 54MHz bus */
+	__raw_writel(0x00000202, LPC17_EMCDYRASCAS(0)); /* 2 CAS, 2 RAS */
+	__raw_writel(0x00000001, LPC17_EMCDYRDCFG);
+	__raw_writel(0x00000000, LPC17_EMCDYTRP);
+	__raw_writel(0x00000002, LPC17_EMCDYRAS);
+	__raw_writel(0x00000003, LPC17_EMCDYSREX);
+	__raw_writel(0x00000001, LPC17_EMCDYAPR);
+	__raw_writel(0x00000002, LPC17_EMCDYDAL);
+	__raw_writel(0x00000001, LPC17_EMCDYWR);
+	__raw_writel(0x00000003, LPC17_EMCDYRC);
+	__raw_writel(0x00000003, LPC17_EMCDYRFC);
+	__raw_writel(0x00000003, LPC17_EMCDYXSR);
+	__raw_writel(0x00000000, LPC17_EMCDYRRD);
+	__raw_writel(0x00000000, LPC17_EMCDYMRD);
+	msdelay(100);
+
+	/* NOP */
+	__raw_writel(0x183, LPC17_EMCDYCTRL);
+	msdelay(200);
+
+	/* Pre-charge all with fast refresh */
+	__raw_writel(0x103, LPC17_EMCDYCTRL);
+	__raw_writel(0x2, LPC17_EMCDYRFSH);
+	msdelay(1);
+
+	/* Set refresh period */
+	__raw_writel(0x2E, LPC17_EMCDYRFSH);
+
+	/* Load mode word, CAS2, burst of 4 */
+	__raw_writel(0x083, LPC17_EMCDYCTRL);
+	tmp32 = __raw_readl(PHYS_SDRAM_1 | (0X22 << 13));
+
+	/* Normal mode */
+	__raw_writel(0x0, LPC17_EMCDYCTRL);
+
+	/* Enable DRAM buffer */
+	__raw_writel(0x00084480, LPC17_EMCDDYCFG(0));
+
+	/* NOR FLASH timing */
+	__raw_writel(0x00000081, LPC17_EMCSTCFG(0));
+	__raw_writel(0x00000002, LPC17_EMCSTWWEN(0));
+	__raw_writel(0x00000002, LPC17_EMCSTWOEN(0));
+	__raw_writel(0x0000001F, LPC17_EMCSTWRD(0));
+	__raw_writel(0x0000001F, LPC17_EMCSTWPAGE(0));
+	__raw_writel(0x0000001F, LPC17_EMCSTWWR(0));
+	__raw_writel(0x0000001F, LPC17_EMCSTWTURN(0));
+
+	/* NAND FLASH timing */
+	__raw_writel(0x00000080, LPC17_EMCSTCFG(1));
+	__raw_writel(0x00000002, LPC17_EMCSTWWEN(1));
+	__raw_writel(0x00000002, LPC17_EMCSTWOEN(1));
+	__raw_writel(0x0000001F, LPC17_EMCSTWRD(1));
+	__raw_writel(0x0000001F, LPC17_EMCSTWPAGE(1));
+	__raw_writel(0x0000001F, LPC17_EMCSTWWR(1));
+	__raw_writel(0x0000001F, LPC17_EMCSTWTURN(1));
+}
+
diff -Naur u-boot-2011.06/board/nxp/ea1788/mpu_setup.c u-boot-2011.06-lpc1788/board/nxp/ea1788/mpu_setup.c
--- u-boot-2011.06/board/nxp/ea1788/mpu_setup.c	1969-12-31 16:00:00.000000000 -0800
+++ u-boot-2011.06-lpc1788/board/nxp/ea1788/mpu_setup.c	2011-08-16 13:52:57.730750261 -0700
@@ -0,0 +1,51 @@
+/*
+ * Copyright (C) 2011 by NXP Semiconductors
+ * All rights reserved.
+ *
+ * @Author: Kevin Wells
+ * @Descr: EA1788 specific MPU setup
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+
+#include "asm/arch-cortex-m3/cortex-m3.h"
+
+/*
+ * Each entry is a region mapped as address/control
+ * Table ends with (-1)
+ */
+const unsigned long board_mpu_table[] = {
+#if 0 /* Just open everything up */
+	0x00000000, CM3_MPU_DATA_RW_RW | CM3_MPU_SHARED | CM3_MPU_SIZE_4GB,
+
+#else /* Limit permissions to regions, but only 8 regions */
+	/* FLASH, IRAM, boot ROM */
+	0x00000000, CM3_MPU_DATA_RW_RW | CM3_MPU_SHARED | CM3_MPU_SIZE_512MB,
+
+	/* On-chip peripheral SRAM banks 0 and 1, AHB and APB peripherals */
+	0x20000000, CM3_MPU_DATA_RW_RW | CM3_MPU_SHARED | CM3_MPU_SIZE_1GB,
+
+	/* NOR and NAND FLASH, DRAM */
+	0x80000000, CM3_MPU_DATA_RW_RW | CM3_MPU_SHARED | CM3_MPU_SIZE_1GB,
+
+	/* Cortex M3 private bus */
+	0xE0000000, CM3_MPU_DATA_RW_RW | CM3_MPU_SHARED | CM3_MPU_SIZE_1MB |
+		CM3_MPU_DIS_INST_FETCHES,
+#endif
+	/* End of table */
+	0xFFFFFFFF
+};
+
diff -Naur u-boot-2011.06/board/nxp/ea1788/nand.c u-boot-2011.06-lpc1788/board/nxp/ea1788/nand.c
--- u-boot-2011.06/board/nxp/ea1788/nand.c	1969-12-31 16:00:00.000000000 -0800
+++ u-boot-2011.06-lpc1788/board/nxp/ea1788/nand.c	2011-08-15 12:33:46.830123983 -0700
@@ -0,0 +1,117 @@
+/*
+ * Copyright (C) 2011 by NXP Semiconductors
+ * All rights reserved.
+ *
+ * @Author: Kevin Wells
+ * @Descr: Simple NAND interface driver
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+
+#if defined(CONFIG_CMD_NAND)
+
+#include <nand.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/lpc17_regs.h>
+
+/* Set this define to 0 to use hardware detection */
+#define USE_NAND_DELAY 0
+
+/*
+ * EA1788 board setup with CS1 as chip select. ALE uses A19, CLE uses A21,
+ * and NAND RDY/BUSY is read on GPIO P2.21. CS1 is controlled as a GPIO
+ * instead of a CS on GPIO P4.31 to lock the CS state during NAND transfers.
+ */
+#define NAND_ALE_OFFS	(1 << 19)
+#define NAND_CLE_OFFS	(1 << 20)
+
+static void ea1788_set_nand_cs(unsigned int set)
+{
+	if (set)
+		lpc17xx_gpio_set_state(4, 31, 1);
+	else
+		lpc17xx_gpio_set_state(4, 31, 0);
+}
+
+static void ea1788_nand_hwcontrol(struct mtd_info *mtd, int cmd,
+	unsigned int ctrl)
+{
+	struct nand_chip *this = mtd->priv;
+	char *pCMD;
+	long IO_ADDR_W;
+
+	if (ctrl & NAND_CTRL_CHANGE) {
+		IO_ADDR_W = (long) this->IO_ADDR_W &
+			~(NAND_CLE_OFFS | NAND_ALE_OFFS);
+
+		if (ctrl & NAND_CLE)
+			IO_ADDR_W |= NAND_CLE_OFFS;
+		else if (ctrl & NAND_ALE)
+			IO_ADDR_W |= NAND_ALE_OFFS;
+
+		if (ctrl & NAND_NCE)
+			ea1788_set_nand_cs(0);
+		else
+			ea1788_set_nand_cs(1);
+
+		this->IO_ADDR_W = (void *) IO_ADDR_W;
+	}
+
+	if (cmd != NAND_CMD_NONE) {
+		pCMD = (char *) this->IO_ADDR_W;
+		*pCMD = cmd;
+	}
+
+	return;
+}
+
+#if USE_NAND_DELAY == 0
+static int ea1788_nand_device_ready(struct mtd_info *mtd)
+{
+	/* If NAND doesn't work, check jumper JP2-3-4 on base board */
+	return lpc17xx_gpio_get_state(2, 21);
+}
+#endif
+
+/*
+ * Setup NAND timing and standard NAND functions
+ */
+int board_nand_init(struct nand_chip *nand)
+{
+	/* Setup CS1 on p4.31 for GPIO output instead of CS1 */
+	lpc17xx_gpio_set_output(4, 31);
+	ea1788_set_nand_cs(1);
+
+	/* P2.21 for NAND ready configured as GPIO input */
+	lpc17xx_gpio_set_input(2, 21);
+
+	nand->cmd_ctrl = ea1788_nand_hwcontrol;
+#if USE_NAND_DELAY == 0
+	nand->dev_ready = ea1788_nand_device_ready;
+#else
+	nand->chip_delay = USE_NAND_DELAY;
+#endif
+	nand->ecc.mode = NAND_ECC_SOFT;
+	nand->options = NAND_USE_FLASH_BBT;
+
+	return 0;
+}
+#endif
diff -Naur u-boot-2011.06/board/nxp/ea1788/net.c u-boot-2011.06-lpc1788/board/nxp/ea1788/net.c
--- u-boot-2011.06/board/nxp/ea1788/net.c	1969-12-31 16:00:00.000000000 -0800
+++ u-boot-2011.06-lpc1788/board/nxp/ea1788/net.c	2011-08-16 15:27:10.550749908 -0700
@@ -0,0 +1,498 @@
+/*
+ * Copyright (C) 2011 by NXP Semiconductors
+ * All rights reserved.
+ *
+ * @Author: Kevin Wells
+ * @Descr: LPC17xx MAC (ethernet) support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <net.h>
+#include <malloc.h>
+#include "miiphy.h"
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/lpc17_regs.h>
+#include <asm/arch/lpc17_clocks.h>
+#include <asm/arch/lpc17_mac.h>
+
+/* Structure of a TX/RX descriptor */
+typedef struct
+{
+  volatile unsigned long packet;
+  volatile unsigned long control;
+} TXRX_DESC_T;
+
+/* Structure of a RX status entry */
+typedef struct
+{
+  volatile unsigned long statusinfo;
+  volatile unsigned long statushashcrc;
+} RX_STATUS_T;
+
+#define USE_PHY_RMII
+#define ENET_MAX_TX_PACKETS	8 /* TX locks when using 4 */
+#define ENET_MAX_RX_PACKETS	8
+#define PHYDEF_PHYADDR		1
+#define ENET_MAXF_SIZE		1536
+#define DP83848_PHY_STATUS	0x10
+
+/*
+ * Buffer storage size, needs space for descriptors, statuses, and data
+ * buffers
+ */
+#define BUFF_SIZE_BYTES		((ENET_MAXF_SIZE * (ENET_MAX_TX_PACKETS + \
+				ENET_MAX_RX_PACKETS)) + 512)
+
+static TXRX_DESC_T *pTXDesc;
+static unsigned long *pTXStatus;
+static unsigned long pTXVBuffs [ENET_MAX_TX_PACKETS];
+static TXRX_DESC_T *pRXDesc;
+static RX_STATUS_T *pRXStatus;
+static unsigned long pRXVBuffs [ENET_MAX_RX_PACKETS];
+static unsigned long *ethbuffs;
+
+#define msDelay(x) udelay(x * 1000)
+
+static int lpc17xx_mii_write(long PhyReg, long Value)
+{
+	long mst = 250;
+	int sts = 0;
+
+	/* Write value at PHY address and register */
+	__raw_writel((PHYDEF_PHYADDR << 8) | PhyReg, MAC_MADR);
+	__raw_writel(Value, MAC_MWTD);
+
+	/* Wait for unbusy status */
+	while (mst > 0) {
+		if ((__raw_readl(MAC_MIND) & 1) == 0) {
+			mst = 0;
+			sts = 1;
+		} else {
+			mst--;
+			msDelay(1);
+		}
+	}
+
+	return sts;
+}
+
+static int lpc17xx_mii_read(unsigned long PhyReg, unsigned long *data) 
+{
+	unsigned long mst = 250;
+	int sts = 0;
+
+	/* Read value at PHY address and register */
+	__raw_writel((PHYDEF_PHYADDR << 8) | PhyReg, MAC_MADR);
+	__raw_writel(1, MAC_MCMD);
+
+	/* Wait for unbusy status */
+	while (mst > 0) {
+		if ((__raw_readl(MAC_MIND) & 1) == 0) {
+			mst = 0;
+			*data = __raw_readl(MAC_MRDD);
+			sts = 1;
+		} else {
+			mst--;
+			msDelay(1);
+		}
+	}
+
+	__raw_writel(0, MAC_MCMD);
+
+	return sts;
+}
+
+static int lpc17xx_phy_reset(void)
+{
+	int goodacc;
+	unsigned long tmp1, mst;
+
+	/* Reset the PHY and wait for reset to complete */
+	goodacc = lpc17xx_mii_write(MII_BMCR, BMCR_RESET);
+	if (goodacc == 0)
+		return 0;
+
+	mst = 400;
+	goodacc = 0;
+	while (mst > 0) {
+		lpc17xx_mii_read(MII_BMCR, &tmp1);
+		if ((tmp1 & BMCR_RESET) == 0) {
+			mst = 0;
+			goodacc = 1;
+		} else {
+			mst--;
+			msDelay(1);
+		}
+	}
+
+	return goodacc;
+}
+
+static int lpc17xx_phy_get_link_status(void)
+{
+        unsigned long status;
+
+        /* Status is read once to clear old link state */
+        lpc17xx_mii_read(MII_BMSR, &status);
+
+        /*
+	 * Wait if the link is up, and autonegotiation is in progress
+	 * (ie - we're capable and it's not done)
+	 */
+        status = 0;
+        lpc17xx_mii_read(MII_BMSR, &status);
+        if ((status & BMSR_LSTATUS) && (status & BMSR_ANEGCAPABLE)
+            && !(status & BMSR_ANEGCOMPLETE)) {
+                int i = 0;
+
+                while (!(status & BMSR_ANEGCOMPLETE)) {
+                        /* Timeout reached */
+                        if (i > 1000) {
+                                error("Phy auto-negotiation timeout\n");
+                                return 1;
+                        }
+
+                        i++;
+                        msDelay(1);   /* 1 ms */
+                        lpc17xx_mii_read(MII_BMSR, &status);
+                }
+                return 0;
+        } else {
+                if (status & BMSR_LSTATUS)
+                        return 0;
+                else
+                        return 1;
+        }
+
+        return 1;
+}
+
+static int txrx_setup(void)
+{
+	int idx;
+	unsigned long *pTXStatusL, pbase1, pbase2, pbase3;
+	TXRX_DESC_T *pTXRXDesc;
+	RX_STATUS_T *pRXStatusL;
+
+	/* Get physical address and size of DMA buffers */
+	ethbuffs = (unsigned long *) malloc(BUFF_SIZE_BYTES);
+	if (!ethbuffs) {
+		error("Error allocating MAC buffers\n");
+		return 0;
+	}
+
+	/* Setup base pointers */
+	pbase1 = (unsigned long) ethbuffs; /* Start of descriptors */
+	pbase2 = pbase1 + 256;  /* Start of statuses */
+	pbase3 = pbase1 + 512; /* Start of buffers */
+
+	/* Setup pointers to TX structures */
+	__raw_writel(pbase1, MAC_TXDESC);
+	__raw_writel(pbase2, MAC_TXSTATUS);
+	__raw_writel(ENET_MAX_TX_PACKETS - 1, MAC_TXDESCNUM);
+
+	/* Save base address of TX descriptor table and TX status */
+	pTXRXDesc = (TXRX_DESC_T *) pbase1;
+	pTXStatusL = (unsigned long *) pbase2;
+	pTXDesc = pTXRXDesc;
+	pTXStatus = pTXStatusL;
+
+	/* Build TX descriptors */
+	for (idx = 0; idx < ENET_MAX_TX_PACKETS; idx++) {
+		pTXRXDesc->packet = pbase3;
+		pTXRXDesc->control = 0;
+
+		debug("TX descriptor @ %08x, buffer @ %08x, status @ %08x\n",
+			pTXRXDesc, pbase3, pTXStatusL);
+
+		/* Statuses are pre-filled to help with debugging */
+		*pTXStatusL = 0xFFFFFFFF;
+
+		/* Save virtual address of buffer */
+		pTXVBuffs [idx] = (unsigned long) pbase3;
+
+		/* Next descriptor and status */
+		pTXRXDesc++;
+		pTXStatusL++;
+		pbase3 += ENET_MAXF_SIZE;
+	}
+
+	/* Setup pointers to RX structures */
+	__raw_writel((long) pTXRXDesc, MAC_RXDESC);
+	__raw_writel((long) pTXStatusL, MAC_RXSTATUS);
+	__raw_writel(ENET_MAX_RX_PACKETS - 1, MAC_RXDESCNUM);
+
+	/* Save base address of RX descriptor table and RX status */
+	pRXDesc = pTXRXDesc;
+	pRXStatus = pRXStatusL = (RX_STATUS_T *) pTXStatusL;
+
+	/* Build RX descriptors */
+	for (idx = 0; idx < ENET_MAX_TX_PACKETS; idx++) {
+		pTXRXDesc->packet = pbase3;
+		pTXRXDesc->control = 0x80000000 | (ENET_MAXF_SIZE - 1);
+
+		debug("RX descriptor @ %08x, buffer @ %08x, status @ %08x\n",
+			pTXRXDesc, pbase3, pRXStatusL);
+
+		/* Statuses are pre-filled to help with debugging */
+		pRXStatusL->statusinfo = 0xFFFFFFFF;
+		pRXStatusL->statushashcrc = 0xFFFFFFFF;
+
+		/* Save virtual address of buffer */
+		pRXVBuffs [idx] = (unsigned long) pbase3;
+
+		/* Next descriptor and status */
+		pTXRXDesc++;
+		pRXStatusL++;
+		pbase3 += ENET_MAXF_SIZE;
+	}
+
+    return 1;
+}
+
+int lpc17xx_eth_deinit(void)
+{
+	/* Reset PHY */
+	(void) lpc17xx_phy_reset();
+
+	/* Reset all MAC logic */
+	__raw_writel(0xCF00, MAC_MAC1);
+	__raw_writel(0x001C, MAC_COMMAND);
+	msDelay(2);
+
+	lpc17_clk_enable(LPC17_CLK_ENET, 0);
+
+	free(ethbuffs);
+
+	return 1;
+}
+
+int lpc17xx_hw_init(void)
+{
+	int btemp;
+	unsigned int duplex, speed;
+	unsigned long tmp1, mst = 250;
+	uchar bd_enetaddr[6];
+
+	/* Get MAC address from environment variable */
+	eth_getenv_enetaddr("ethaddr", bd_enetaddr);
+
+	/* Enable MII clocking */
+	lpc17_clk_enable(LPC17_CLK_ENET, 1);
+
+	/* Set RMII management clock rate */
+	__raw_writel((7 << 2), MAC_MCFG);
+
+	/* Reset all MAC logic */
+	__raw_writel(0xCF00, MAC_MAC1);
+	__raw_writel(0x0038, MAC_COMMAND);
+	msDelay(10);
+
+	/* Initial MAC initialization */
+	__raw_writel(0x0002, MAC_MAC1);
+	__raw_writel(0x0030, MAC_MAC2);
+	__raw_writel(ENET_MAXF_SIZE, MAC_MAXF);
+
+	/* Maximum number of retries, 0x37 collision window, gap */
+	__raw_writel(0xF | (0x37 << 8), MAC_CLRT);
+	__raw_writel(0x12, MAC_IPGR);
+
+#ifdef USE_PHY_RMII
+	/* RMII setup */
+	__raw_writel(0x240, MAC_COMMAND);
+	__raw_writel(0x000, MAC_SUPP);
+	msDelay(10);
+#else
+	/* MII setup */
+	__raw_writel(0x040, MAC_COMMAND);
+#endif
+
+	/* Enable rate auto-negotiation for the link */
+	if (lpc17xx_mii_write(MII_BMCR,
+		(BMCR_SPEED100 | BMCR_ANENABLE)) == 0)
+		return 0;
+
+	mst = 1000;
+        btemp = 1;
+        while (mst > 0) {
+                /* Wait for Link status to set UP or Timeout */
+                if (lpc17xx_phy_get_link_status() == 0) {
+                        mst = 0;
+                        btemp = 0;
+                        debug("ENET: auto-negotiation complete\n");
+                } else {
+                        mst--;
+                        msDelay(1);
+                }
+        }
+
+        if (btemp) {
+                debug("ENET: auto-negotiation failed\n");
+                return 0;
+        }
+
+        /* Read PHY Status Register to determine Ethernet Configuration */
+        tmp1 = 0;
+        lpc17xx_mii_read(DP83848_PHY_STATUS, &tmp1);
+        duplex = (tmp1 & 0x0004) >> 2;
+        speed = (tmp1 & 0x0002) >> 1;
+
+	/* Configure Full/Half Duplex mode */
+	if (duplex == 1) {
+		/* Full duplex is supported */
+		__raw_writel(__raw_readl(MAC_MAC2) | 1, MAC_MAC2);
+		__raw_writel(__raw_readl(MAC_COMMAND) | (1 << 10),
+			MAC_COMMAND);
+		__raw_writel(0x15, MAC_IPGT);
+		debug("ENET: Full duplex\n");
+	} else {
+		__raw_writel(0x12, MAC_IPGT);
+		debug("ENET: Half duplex\n");
+	}
+
+	/* Configure 100MBit/10MBit mode */
+	if (speed == 0) {
+		/* 100MBase mode */
+		__raw_writel((1 << 8), MAC_SUPP);
+		debug("ENET: 100MBaseT\n");
+	} else 	{
+		/* 10MBase mode */
+		__raw_writel(0, MAC_SUPP);
+		debug("ENET: 10BaseT\n");
+	}
+
+	/* Save station address */
+	__raw_writel((unsigned long) (bd_enetaddr[0] |
+		(bd_enetaddr[1] << 8)), MAC_SA2);
+	__raw_writel((unsigned long) (bd_enetaddr[2] |
+		(bd_enetaddr[3] << 8)), MAC_SA1);
+	__raw_writel((unsigned long) (bd_enetaddr[4] |
+		(bd_enetaddr[5] << 8)), MAC_SA0);
+
+	/* Setup TX and RX descriptors */
+	if (!txrx_setup()) {
+		error("Error initializing MAC buffers\n");
+		lpc17xx_eth_deinit();
+		return 0;
+	}
+
+	/* Enable broadcast and matching address packets */
+	__raw_writel(0x22, MAC_RXFILTCTRL);
+
+	/* Clear and enable interrupts */
+	__raw_writel(0xFFFF, MAC_INTCLR);
+	__raw_writel(0x0, MAC_INTENAB);
+
+	/* Enable receive and transmit mode of MAC ethernet core */
+	__raw_writel(__raw_readl(MAC_COMMAND) | 0x03, MAC_COMMAND);
+	__raw_writel(__raw_readl(MAC_MAC1) | 1, MAC_MAC1);
+
+	/*
+	 * Perform a 'dummy' send of the first ethernet frame with a size of 4
+	 * to 'prime' the MAC.
+	 */
+	tmp1 = 0;
+	eth_send(&tmp1, 4);
+
+	return 1;
+}
+
+void eth_halt(void)
+{
+	lpc17xx_eth_deinit();
+}
+
+int eth_init(bd_t *bd)
+{
+	/* De-init if an error occurred */
+	if (lpc17xx_hw_init() == 0) {
+		error("ENET init failure\n");
+		lpc17xx_eth_deinit();
+		return -1;
+	}
+
+	return 0;
+}
+
+int eth_rx(void)
+{
+	unsigned long idx, length;
+
+	/* Determine if a frame has been received */
+	length = 0;
+	idx = __raw_readl(MAC_RXCONSIDX);
+	if (__raw_readl(MAC_RXPRODIDX) != idx) {
+		/* Clear interrupt */
+		__raw_writel((1 << 3), MAC_INTCLR);
+
+		/* Frame received, get size of RX packet */
+		length = pRXStatus[idx].statusinfo & 0x7FF;
+
+		/* Pass the packet up to the protocol layer */
+		if (length > 0) {
+		        memcpy((void *) NetRxPackets[0], (void *) pRXVBuffs [idx], length);
+			NetReceive(NetRxPackets[0], (unsigned short) length);
+		}
+
+		/* Return DMA buffer */
+		idx++;
+		if (idx >= ENET_MAX_RX_PACKETS)
+			idx = 0;
+
+		__raw_writel(idx, MAC_RXCONSIDX);
+	}
+
+	return (int) length;
+}
+
+int eth_send(volatile void *packet, int length)
+{
+	unsigned long idx, cidx, fb;
+
+	/* Determine number of free buffers and wait for a buffer if needed */
+	fb = 0;
+	while (fb == 0)	{
+		idx = __raw_readl(MAC_TXPRODIDX);
+		cidx = __raw_readl(MAC_TXCONSIDX);
+
+		if (idx == cidx)
+			fb = ENET_MAX_TX_PACKETS;
+		else if (cidx > idx)
+			fb = (ENET_MAX_TX_PACKETS - 1) -
+				((idx + ENET_MAX_TX_PACKETS) - cidx);
+		else
+			fb = (ENET_MAX_TX_PACKETS - 1) - (cidx - idx);
+	}
+
+	/* Update descriptor with new frame size */
+	pTXDesc[idx].control = (length | 0x40000000);
+
+	/* Move data to buffer */
+	memcpy((void *) pTXVBuffs [idx], (void *)packet, length);
+
+	/* Get next index for transmit data DMA buffer and descriptor */
+	idx++;
+	if (idx >= ENET_MAX_TX_PACKETS)
+		idx = 0;
+
+	__raw_writel(idx, MAC_TXPRODIDX);
+
+	return 0;
+}
+
diff -Naur u-boot-2011.06/board/nxp/ea1788/pins.c u-boot-2011.06-lpc1788/board/nxp/ea1788/pins.c
--- u-boot-2011.06/board/nxp/ea1788/pins.c	1969-12-31 16:00:00.000000000 -0800
+++ u-boot-2011.06-lpc1788/board/nxp/ea1788/pins.c	2011-08-12 16:47:55.860749848 -0700
@@ -0,0 +1,1285 @@
+/*
+ * Copyright (C) 2011 by NXP Semiconductors
+ * All rights reserved.
+ *
+ * @Author: Kevin Wells
+ * @Descr: EA1788 board specific pin (IOCON) setup
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/lpc17_regs.h>
+#include <asm/arch/lpc17_iocon.h>
+
+extern void _start(void);
+
+/*
+ * This array maps the LPC1788 pins to the function they are used for on
+ * the EA1788 board. Only pins that change from the default functions are
+ * in this array. To save memory, the array structures are bit packed in
+ * the structure definition. Each entry should only use 32-bits.
+ *
+ */
+const iocon_pin_type ea1788_iocon_pins[] = {
+	{
+		/* P0.0 (D) = CAN_RD1 */
+		0, 0, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 1,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 0,
+			.od	= 0
+		}
+	},
+	{
+		/* P0.1 (D) = CAN_TD1 */
+		0, 1, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 1,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 0,
+			.od	= 0
+		}
+	},
+	{
+		/* P0.2 (D) = UART0 TXD */
+		0, 2, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 1,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 0,
+			.od	= 0
+		}
+	},
+	{
+		/* P0.3 (D) = UART0 RXD */
+		0, 3, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 1,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 0,
+			.od	= 0
+		}
+	},
+	{
+		/* P0.4 (D) = I2S RX clock (alternate LCD D0 when bpp > 16) */
+		0, 4, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 1,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 0,
+			.od	= 0
+		}
+	},
+	{
+		/* P0.5 (D) = I2S RX WS (alternate LCD D1 when bpp > 16) */
+		0, 5, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 1,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 0,
+			.od	= 0
+		}
+	},
+	{
+		/* P0.6 (D) = I2S RX SDA (alternate LCD D8 when bpp > 16) */
+		0, 6, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 1,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 0,
+			.od	= 0
+		}
+	},
+	{
+		/* P0.10 (D) = U2_TXD */
+		0, 10, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 1,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 0,
+			.od	= 0
+		}
+	},
+	{
+		/* P0.11 (D) = U2_RXD */
+		0, 11, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 1,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 0,
+			.od	= 0
+		}
+	},
+	{
+		/* P0.14 (D) = (USB_CONNECT2) USB2 device pullup */
+		0, 14, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 3,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 0,
+			.od	= 0
+		}
+	},
+	{
+		/* P0.15 (D) = SSP0_CLK */
+		0, 15, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 1,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 0,
+			.od	= 0
+		}
+	},
+	{
+		/* P0.16 (D) = SSP0_SSEL */
+		0, 16, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 1,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 0,
+			.od	= 0
+		}
+	},
+	{
+		/* P0.17 (D) = SSP0_MISO */
+		0, 17, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 1,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 0,
+			.od	= 0
+		}
+	},
+	{
+		/* P0.18 (D) = SSP0_MOSI */
+		0, 18, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 1,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 0,
+			.od	= 0
+		}
+	},
+	{
+		/* P0.19 (D) = LCD SPI CS (GPO) */
+		0, 19, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 0,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 0,
+			.od	= 0
+		}
+	},
+	{
+		/* P0.20 (D) = Touchscreen SPI CS (GPO) */
+		0, 20, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 0,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 0,
+			.od	= 0
+		}
+	},
+	{
+		/* P0.21 (D) = GPIO */
+		0, 21, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 0,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 0,
+			.od	= 0
+		}
+	},
+	{
+		/* P0.22 (D) = GPIO */
+		0, 22, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 0,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 0,
+			.od	= 0
+		}
+	},
+	{
+		/* P1.0 (D) = RMII ENET_TXD0 */
+		1, 0, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 1,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 1,
+			.od	= 0
+		}
+	},
+	{
+		/* P1.1 (D) = RMII ENET_TXD1 */
+		1, 1, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 1,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 1,
+			.od	= 0
+		}
+	},
+	{
+		/* P1.2 (D) = SD_CLK */
+		1, 2, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 2,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 0,
+			.od	= 0
+		}
+	},
+	{
+		/* P1.3 (D) = SD_CMD */
+		1, 3, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 2,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 0,
+			.od	= 0
+		}
+	},
+	{
+		/* P1.4 (D) = RMII ENET_TX_EN */
+		1, 4, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 1,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 1,
+			.od	= 0
+		}
+	},
+	{
+		/* P1.5 (D) = SD_PWR */
+		1, 5, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 2,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 0,
+			.od	= 0
+		}
+	},
+	{
+		/* P1.6 (D) = SD_DAT0 */
+		1, 6, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 2,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 0,
+			.od	= 0
+		}
+	},
+	{
+		/* P1.7 (D) = SD_DAT1 */
+		1, 7, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 2,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 0,
+			.od	= 0
+		}
+	},
+	{
+		/* P1.8 (D) = RMII CRS */
+		1, 8, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 1,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 1,
+			.od	= 0
+		}
+	},
+	{
+		/* P1.9 (D) = RMII RXD0 */
+		1, 9, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 1,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 1,
+			.od	= 0
+		}
+	},
+	{
+		/* P1.10 (D) = RMII RXD1 */
+		1, 10, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 1,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 1,
+			.od	= 0
+		}
+	},
+	{
+		/* P1.11 (D) = SD_DAT2 */
+		1, 11, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 2,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 0,
+			.od	= 0
+		}
+	},
+	{
+		/* P1.12 (D) = SD_DAT3 */
+		1, 12, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 2,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 0,
+			.od	= 0
+		}
+	},
+	{
+		/* P1.13 (D) = GPIO */
+		1, 13, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 0,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 0,
+			.od	= 0
+		}
+	},
+	{
+		/* P1.14 (D) = RMII RXER */
+		1, 14, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 1,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 0,
+			.od	= 0
+		}
+	},
+	{
+		/* P1.15 (D) = RMII CLK */
+		1, 15, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 1,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 0,
+			.od	= 0
+		}
+	},
+	{
+		/* P1.16 (D) = RMII MCD */
+		1, 16, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 1,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 0,
+			.od	= 0
+		}
+	},
+	{
+		/* P1.17 (D) = RMII MDIO */
+		1, 17, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 1,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 0,
+			.od	= 0
+		}
+	},
+	{
+		/* P1.18 (D) = GPIO */
+		1, 18, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 0,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 0,
+			.od	= 0
+		}
+	},
+	{
+		/* P1.19 (D) = USB1-PWREN */
+		1, 19, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 2,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 0,
+			.od	= 0
+		}
+	},
+	{
+		/* P1.20 (D) = LCD D10 */
+		1, 20, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 7,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 0,
+			.od	= 0
+		}
+	},
+	{
+		/* P1.21 (D) = LCD D11 */
+		1, 21, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 7,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 0,
+			.od	= 0
+		}
+	},
+	{
+		/* P1.22 (D) = LCD D12 */
+		1, 22, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 7,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 0,
+			.od	= 0
+		}
+	},
+	{
+		/* P1.23 (D) = LCD D13 */
+		1, 23, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 7,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 0,
+			.od	= 0
+		}
+	},
+	{
+		/* P1.24 (D) = LCD D14 */
+		1, 24, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 7,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 0,
+			.od	= 0
+		}
+	},
+	{
+		/* P1.25 (D) = LCD D15 */
+		1, 25, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 7,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 0,
+			.od	= 0
+		}
+	},
+	{
+		/* P1.26 (D) = LCD D20 */
+		1, 26, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 7,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 0,
+			.od	= 0
+		}
+	},
+	{
+		/* P1.27 (D) = USB transceiver INT (MIC2555) */
+		1, 27, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 1,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 0,
+			.od	= 0
+		}
+	},
+	{
+		/* P1.28 (D) = USB I2C SCL */
+		1, 28, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 1,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 0,
+			.od	= 0
+		}
+	},
+	{
+		/* P1.29 (D) = USB I2C SDA */
+		1, 29, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 1,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 0,
+			.od	= 0
+		}
+	},
+	{
+		/* P2.0 (D) = LCDPWR */
+		2, 0, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 7,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 0,
+			.od	= 0
+		}
+	},
+	{
+		/* P2.1 (D) = LCDLE */
+		2, 1, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 7,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 0,
+			.od	= 0
+		}
+	},
+	{
+		/* P2.2 (D) = LCDDCLK */
+		2, 2, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 7,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 0,
+			.od	= 0
+		}
+	},
+	{
+		/* P2.3 (D) = LCDFP */
+		2, 3, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 7,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 0,
+			.od	= 0
+		}
+	},
+	{
+		/* P2.4 (D) = LCDENAB */
+		2, 4, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 7,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 0,
+			.od	= 0
+		}
+	},
+	{
+		/* P2.5 (D) = LCDLP */
+		2, 5, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 7,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 0,
+			.od	= 0
+		}
+	},
+	{
+		/* P2.6 (D) = LCD D4 */
+		2, 6, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 7,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 0,
+			.od	= 0
+		}
+	},
+	{
+		/* P2.7 (D) = LCD D5 */
+		2, 7, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 7,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 0,
+			.od	= 0
+		}
+	},
+	{
+		/* P2.8 (D) = LCD D6 */
+		2, 8, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 7,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0, IOCON_D_TYPE,
+			.slew	= 0,
+			.od	= 0
+		}
+	},
+	{
+		/* P2.9 (D) = LCD D7 */
+		2, 9, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 7,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 0,
+			.od	= 0
+		}
+	},
+	{
+		/* P2.10 (D) = GPIO (LED and SW6) */
+		2, 10, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 0,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 0,
+			.od	= 0
+		}
+	},
+	{
+		/* P2.11 (D) = LCD clock in */
+		2, 11, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 7,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 0,
+			.od	= 0
+		}
+	},
+	{
+		/* P2.12 (D) = LCD D18 */
+		2, 12, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 7,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 0,
+			.od	= 0
+		}
+	},
+	{
+		/* P2.13 (D) = LCD D19 */
+		2, 13, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 7,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 0,
+			.od	= 0
+		}
+	},
+	{
+		/* P2.14 (D) = GPIO */
+		2, 14, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 0,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 0,
+			.od	= 0
+		}
+	},
+	{
+		/* P2.15 (D) = GPIO */
+		2, 15, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 0,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 0,
+			.od	= 0
+		}
+	},
+	{
+		/* P2.16 (D) = EMC CAS */
+		2, 16, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 1,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 1,
+			.od	= 0
+		}
+	},
+	{
+		/* P2.17 (D) = EMC RAS */
+		2, 17, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 1,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 1,
+			.od	= 0
+		}
+	},
+	{
+		/* P2.18 (D) = EMC CLK0 */
+		2, 18, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 1,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 1,
+			.od	= 0
+		}
+	},
+	{
+		/* P2.19 (D) = GPIO */
+		2, 19, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 0,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 0,
+			.od	= 0
+		}
+	},
+	{
+		/* P2.20 (D) = EMC DYCS0 */
+		2, 20, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 1,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 1,
+			.od	= 0
+		}
+	},
+	{
+		/* P2.21 (D) = GPIO */
+		2, 21, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 0,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 0,
+			.od	= 0
+		}
+	},
+	{
+		/* P2.22 (D) = GPI 5-key joystick */
+		2, 22, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 0,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 0,
+			.od	= 0
+		}
+	},
+	{
+		/* P2.23 (D) = GPI 5-key joystick */
+		2, 23, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 0,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 0,
+			.od	= 0
+		}
+	},
+	{
+		/* P2.24 (D) = EMC CKE0 */
+		2, 24, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 1,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 1,
+			.od	= 0
+		}
+	},
+	{
+		/* P2.25 (D) = GPI 5-key joystick */
+		2, 25, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 0,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 0,
+			.od	= 0
+		}
+	},
+	{
+		/* P2.26 (D) = GPI 5-key joystick */
+		2, 26, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 0,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 0,
+			.od	= 0
+		}
+	},
+	{
+		/* P2.27 (D) = GPI 5-key joystick */
+		2, 27, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 0,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 0,
+			.od	= 0
+		}
+	},
+	{
+		/* P2.28 (D) = DQM0 */
+		2, 28, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 1,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 1,
+			.od	= 0
+		}
+	},
+	{
+		/* P2.29 (D) = DQM1 */
+		2, 29, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 1,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 1,
+			.od	= 0
+		}
+	},
+	{
+		/* P2.30 (D) = DQM2 */
+		2, 30, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 1,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 1,
+			.od	= 0
+		}
+	},
+	{
+		/* P2.31 (D) = DQM3 */
+		2, 31, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 1,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 1,
+			.od	= 0
+		}
+	},
+	{
+		/* P5.0 (D) = GPIO */
+		5, 0, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 0,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 0,
+			.od	= 0
+		}
+	},
+	{
+		/* P5.1 (D) = GPIO */
+		5, 1,
+		.iocon.d = {
+			.func	= 0,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 0,
+			.od	= 0
+		}
+	},
+	{
+		/* P5.2 (I) = GPIO */
+		5, 2, IOCON_I_TYPE,
+		.iocon.i = {
+			.func	= 0,
+			.inv	= 0,
+			.hs	= 0,
+			.hidrive = 0,
+		}
+	},
+	{
+		/* P5.3 (I) = GPIO */
+		5, 3, IOCON_I_TYPE,
+		.iocon.i = {
+			.func	= 0,
+			.inv	= 0,
+			.hs	= 0,
+			.hidrive = 0,
+		}
+	},
+	{
+		/* P5.4 (D) = GPIO */
+		5, 4, IOCON_D_TYPE,
+		.iocon.d = {
+			.func	= 0,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 0,
+			.od	= 0
+		}
+	},
+	{
+		/* P0.7 (W) = I2S TX SCK */
+		0, 7, IOCON_W_TYPE,
+		.iocon.w = {
+			.func	= 1,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.filter	= 0,
+			.slew	= 0,
+			.od	= 0
+		}
+	},
+	{
+		/* P0.8 (W) = I2S TX WS */
+		0, 8, IOCON_W_TYPE,
+		.iocon.w = {
+			.func	= 1,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.filter	= 0,
+			.slew	= 0,
+			.od	= 0
+		}
+	},
+	{
+		/* P0.9 (W) = I2S TX SDA */
+		0, 9, IOCON_W_TYPE,
+		.iocon.w = {
+			.func	= 1,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.filter	= 0,
+			.slew	= 0,
+			.od	= 0
+		}
+	},
+	{
+		/* P0.12 (A) = USB2 PWREN */
+		0, 12, IOCON_A_TYPE,
+		.iocon.a = {
+			.func	= 1,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.admode = 0,
+			.filter	= 0,
+			.od	= 0,
+			.dacen	= 0
+		}
+	},
+	{
+		/* P0.13 (A) = USB2 UPLED */
+		0, 13, IOCON_A_TYPE,
+		.iocon.a = {
+			.func	= 1,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.admode = 0,
+			.filter	= 0,
+			.od	= 0,
+			.dacen	= 0
+		}
+	},
+	{
+		/* P0.23 (A) = GPIO or AIN0 */
+		0, 23, IOCON_A_TYPE,
+		.iocon.a = {
+			.func	= 1,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.admode = 1,
+			.filter	= 0,
+			.od	= 0,
+			.dacen	= 0
+		}
+	},
+	{
+		/* P0.24 (A) = GPIO or AIN1 */
+		0, 24, IOCON_A_TYPE,
+		.iocon.a = {
+			.func	= 1,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.admode = 1,
+			.filter	= 0,
+			.od	= 0,
+			.dacen	= 0
+		}
+	},
+	{
+		/* P0.25 (A) = GPIO or AIN2 */
+		0, 25, IOCON_A_TYPE,
+		.iocon.a = {
+			.func	= 1,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.admode = 1,
+			.filter	= 0,
+			.od	= 0,
+			.dacen	= 0
+		}
+	},
+	{
+		/* P0.26 (A) = GPO or AOUT */
+		0, 26, IOCON_A_TYPE,
+		.iocon.a = {
+			.func	= 2,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.admode = 1,
+			.filter	= 0,
+			.od	= 0,
+			.dacen	= 1
+		}
+	},
+	{
+		/* P0.27 (I) = I2C SCL */
+		0, 27, IOCON_I_TYPE,
+		.iocon.i = {
+			.func	= 1,
+			.inv	= 0,
+			.hs	= 1,
+			.hidrive = 1,
+		}
+	},
+	{
+		/* P0.28 (I) = I2C SDA */
+		0, 28, IOCON_I_TYPE,
+		.iocon.i = {
+			.func	= 1,
+			.inv	= 0,
+			.hs	= 1,
+			.hidrive = 1,
+		}
+	},
+	{
+		/* P0.29 (U) = USB1 DP */
+		0, 29, IOCON_U_TYPE,
+		.iocon.u = {
+			.func	= 1,
+		}
+	},
+	{
+		/* P0.30 (U) = USB2 DP */
+		0, 30, IOCON_U_TYPE,
+		.iocon.u = {
+			.func	= 1,
+		}
+	},
+	{
+		/* P0.31 (U) = USB1 DM */
+		0, 31, IOCON_U_TYPE,
+		.iocon.u = {
+			.func	= 1,
+		}
+	},
+	{
+		/* P1.30 (D) = USB2 VBUS */
+		0, 30, IOCON_D_TYPE,
+		.iocon.a = {
+			.func	= 2,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.admode = 0,
+			.filter	= 0,
+			.od	= 0,
+			.dacen	= 0
+		}
+	},
+	{
+		/* P1.31 (D) = USB2 OVRCR */
+		0, 31, IOCON_D_TYPE,
+		.iocon.a = {
+			.func	= 1,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.admode = 0,
+			.filter	= 0,
+			.od	= 0,
+			.dacen	= 0
+		}
+	}
+};
+
+void ea1788_setup_pins(void)
+{
+	int idx;
+	u16 pin, grp;
+	iocon_pin_type *pi, ea1788_addr_data_pin = {
+		0, 0,
+		.iocon.d = {
+			.func	= 1,
+			.mode	= LPC17_NO_PULLUP,
+			.hys	= 0,
+			.inv	= 0,
+			.slew	= 1,
+			.od	= 0
+		}
+	};
+
+	/* Setup data, address, and EMC control pins */
+	for (grp = 3; grp <= 4; grp++) {
+		for (pin = 0; pin <= 31; pin++) {
+			ea1788_addr_data_pin.grp = grp;
+			ea1788_addr_data_pin.pin = pin;
+			lpc17_iocon_setup(&ea1788_addr_data_pin);
+		}
+	}
+
+	/*
+	 * The pointer to the pin setup table may be in RAM, but we might be
+	 * running from FLASH. Manually fixup the pointer to the table to
+	 * point to the relative location to the start of code (_start)
+	 */
+	pi = (iocon_pin_type *) ((u32) ea1788_iocon_pins -
+		(u32) _start);
+
+	for (idx = 0; idx < ARRAY_SIZE(ea1788_iocon_pins); idx++)
+		lpc17_iocon_setup(&pi[idx]);
+}
+
diff -Naur u-boot-2011.06/include/configs/ea1788.h u-boot-2011.06-lpc1788/include/configs/ea1788.h
--- u-boot-2011.06/include/configs/ea1788.h	1969-12-31 16:00:00.000000000 -0800
+++ u-boot-2011.06-lpc1788/include/configs/ea1788.h	2011-08-16 10:03:19.860159459 -0700
@@ -0,0 +1,311 @@
+#ifndef __EA1788_H
+#define __EA1788_H
+
+/*
+ * Copyright (C) 2011 by NXP Semiconductors
+ * All rights reserved.
+ *
+ * @Author: Kevin Wells
+ * @Descr: Board specific u-boot configuration for the EA1788 board
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+/*
+ * This should be setup to the board specific rate for the external oscillator
+ */
+#define CONFIG_LPC17_OSC_RATE		12000000
+
+/*
+ * SYSCLK setup. Set the CONFIG_LPC17_PLL0_USE_EXTOSC define to 1 to
+ * use the external oscillator for the SYSCLK rate. Otherwise, the internal
+ * oscillator is used as SYSCLK.
+ */
+#define CONFIG_LPC17_PLL0_USE_EXTOSC	1
+
+/*
+ * Set CONFIG_LPC17_PLL0_ENABLE to 1 to enable PLL0. If PLL0 is enabled,
+ * the values of CONFIG_LPC17_PLL0_M and CONFIG_LPC17_PLL0_P must also
+ * be setup to configure the PLL0 rate based on the selected input clock.
+ * See the LCP177x/lpc178x User's Manual for information on setting these
+ * values correctly. SYSCLK is used as the PLL0 input clock.
+ * 
+ * If CONFIG_LPC17_PLL0_USE_EXTOSC==1
+ *  PLL0_CLK_OUT = CONFIG_LPC17_PLL0_M * CONFIG_LPC17_OSC_RATE
+ * else
+ *  PLL0_CLK_OUT = CONFIG_LPC17_PLL0_M * 12000000 (internal oscillator)
+ * 
+ * PLL0_FCCO mist be between 156MHz and 320MHz
+ *  where PLL0_FFC0 = PLL0_CLK_OUT * 2 * CONFIG_LPC17_PLL0_P
+ * PLL0_CLK_OUT must be between 9.75MHz and 160MHz
+ */
+#define CONFIG_LPC17_PLL0_ENABLE	1
+#define CONFIG_LPC17_PLL0_M		9
+#define CONFIG_LPC17_PLL0_P		1
+
+/*
+ * Set CONFIG_LPC17_PLL1_ENABLE to 1 to enable PLL1. If PLL1 is enabled,
+ * the values of CONFIG_LPC17_PLL1_M and CONFIG_LPC17_PLL1_P must also
+ * be setup to configure the PLL1 rate based on the selected input clock.
+ * 
+ * PLL1_CLK_OUT = CONFIG_LPC17_PLL1_M * CONFIG_LPC17_OSC_RATE
+ * PLL1_FFC0 = PLL1_CLK_OUT * 2 * CONFIG_LPC17_PLL1_P
+ * 
+ * PLL1_FCCO mist be between 156MHz and 320MHz
+ * PLL1_CLK_OUT must be between 9.75MHz and 160MHz
+ *  48MHz for USB, or anything if routed to the CLKOUT pin
+ */
+#define CONFIG_LPC17_PLL1_ENABLE	1
+#define CONFIG_LPC17_PLL1_M		4
+#define CONFIG_LPC17_PLL1_P		2
+
+/*
+ * Set CONFIG_LPC17_PLL0_FOR_CPU to 1 to use the PLL0 out for the CPU divider
+ * clock. If not set, SYSCLK is used as the CPU divider clock. Select a value
+ * between 1 and 31 for the CONFIG_LPC17_CPU_DIV value. The CPU clock will be
+ * either the PLL0 clock or the SYSCLK divided by the divider.
+ */
+#define CONFIG_LPC17_PLL0_FOR_CPU	1
+#define CONFIG_LPC17_CPU_DIV		1
+
+/*
+ * If using USB, PLL1 is used for the USB clock and needs to be 48MHz. Set
+ * this value to the divider from the PLL1 clock rate to get 48MHz. If not
+ * using USB, set this to 0. Only dividers of 4 and 6 are supported, which
+ * map to PLL1 rates of 192MHz and 288MHz, respectively.
+ */
+#define CONFIG_LPC17_USB_DIV		4
+
+/*
+ * The EMC clock is at the CPU rate or 1/2 the CPU rate. Set this value to 1
+ * to use half the CPU clock for the EMC rate
+*/
+#define CONFIG_LPC17_EMC_HALFCPU	1
+
+/*
+ * Peripheral clock selector. This divider, between 1 and 31, is used to
+ * generate the clock to the peripherals. The rate is divided from the CPU
+ * clock.
+ */
+#define CONFIG_LPC17_PCLK_DIV		2
+
+/*
+ * Number of FLASH clocks for the FLASH accelerator, must be between 1 and
+ * 6. See the User's Manual for the correct setting based on your CPU clock
+ * rate.
+ */
+#define CONFIG_LPC17_FLASH_CLOCKS	6
+
+/*
+ * select the UART used on the board. Five UARTs are available labelled
+ * UART0 to UART4. Select 0 to 4 for the UART used for uboot.
+ */
+#define CONFIG_LPC17_UART_BOOT		0
+
+/*
+ * Linux machine type, reuse the 24xx machine ID
+ */
+#define CONFIG_LPC17XX_MACHID		MACH_TYPE_LPC24XX
+
+/*
+ * LPC1788 built-in FLASH
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	32
+#define CONFIG_SYS_FLASH_BASE		0x00000000
+
+/*
+ * CPU options
+ */
+#define CONFIG_ARM_THUMB		1
+#define CONFIG_LPC17XX
+#define CONFIG_SYS_NO_ICACHE		1
+#define CONFIG_SYS_NO_DCACHE		1
+
+/*
+ * If the CONFIG_USE_BOARD_MPU_TABLE is defined, a MPU setup table needs
+ * to be setup for the board that initializes the MPU permissions. If
+ * this is undefined, the MPU will be setup with RW for the entire address
+ * range.
+ */
+#define CONFIG_USE_BOARD_MPU_TABLE
+
+/*
+ * Needed for board init
+ */
+#undef CONFIG_SKIP_LOWLEVEL_INIT
+
+/*
+ * Use red LED for status
+ */
+#define STATUS_LED_RED
+
+/*
+ * SDRAM physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM_1			0xA0000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE		0x02000000 /* 32 MB SDRAM */
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+
+/*
+ * 2KHz clock tick
+ */
+#define	CONFIG_SYS_HZ			1000
+#define CONFIG_SYS_SYS_CLK_FREQ		CONFIG_SYSPLL_CLK_RATE
+
+/*
+ * Address and size of stored environment Data
+ */
+#define CONFIG_ENV_IS_IN_NAND		1
+#define CONFIG_ENV_SIZE			0x40000 /* 2 blocks */
+#define CONFIG_ENV_OFFSET		0x40000 /* Blocks 2, 3 */
+#define CONFIG_ENV_ADDR			0xA0000100 /* ATAGs passed here */
+
+/*
+ * Area and size for malloc
+ */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 1024 * 1024)
+
+/*
+ * No support for IRQs
+ */
+#undef CONFIG_USE_IRQ
+
+/*
+ * Stack size and global data size
+ */
+#define CONFIG_STACKSIZE		(32 * 1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	128
+
+/*
+ * ATAG support
+ */
+#define CONFIG_CMDLINE_TAG		1
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+
+/*
+ * System UART selection, valid selections include 0, 1, 2, 3
+ */
+#define CONFIG_LPC17XX_UART		0 /* 0 - 3 */
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{9600, 19200, 38400, 57600, 115200}
+
+/*
+ * Default load address for programs
+ */
+#define CONFIG_SYS_LOAD_ADDR		0xA0100000
+
+/*
+ * Default boot delay is 3 seconds
+ */
+#define CONFIG_BOOTDELAY		3
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+/*
+ * Prompt and command buffer setup
+ */
+#define CONFIG_SYS_LONGHELP
+#define	CONFIG_SYS_CBSIZE		256
+#define	CONFIG_SYS_PROMPT		"uboot> "
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define	CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+/*
+ * Default range for the memory tests
+ */
+#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_1
+#define CONFIG_SYS_MEMTEST_END		(PHYS_SDRAM_1 + 0x01000000)
+
+/*
+ * Support for NAND FLASH, environment store in NAND at block 100
+ */
+#define CONFIG_CMD_NAND
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		0x90000000
+
+/* allow to overwrite serial and ethaddr */
+//#define CONFIG_ENV_OVERWRITE
+
+/*
+ * Support for various capabilities
+ */
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_LOADS_BAUD_CHANGE
+
+/*
+ * Network setup
+ */
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_IPADDR		192.168.1.101
+#define CONFIG_SERVERIP		192.168.1.41
+#define CONFIG_GATEWAYIP	192.168.1.1
+#define CONFIG_ETHADDR		00:E0:0C:00:00:01
+
+#define CONFIG_BOOTFILE		uImage
+#define CONFIG_LOADADDR		0xA0100000
+#define CONFIG_ROOTPATH		/home/user/dev/rootfs
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/*
+ * Other commands
+ */
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_ELF
+#undef CONFIG_CMD_MISC
+#define CONFIG_MISC_INIT_R
+
+/*
+ * Initial data areas
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR 0x10000000
+#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_INIT_RAM_ADDR + \
+	CONFIG_SYS_GBL_DATA_OFFSET)
+
+/*
+ * Misc
+ */
+#define CONFIG_DISPLAY_CPUINFO
+
+#endif /* __EA1788_H */
diff -Naur u-boot-2011.06/Makefile u-boot-2011.06-lpc1788/Makefile
--- u-boot-2011.06/Makefile	2011-06-27 13:22:42.000000000 -0700
+++ u-boot-2011.06-lpc1788/Makefile	2011-07-26 15:48:32.605232966 -0700
@@ -356,11 +356,20 @@
 ALL += $(obj)mmc_spl/u-boot-mmc-spl.bin
 endif
 
+# LPC addition, could use a conditional
+ALL += u-boot-lpc.hex u-boot.dis
+
 all:		$(ALL)
 
 $(obj)u-boot.hex:	$(obj)u-boot
 		$(OBJCOPY) ${OBJCFLAGS} -O ihex $< $@
 
+$(obj)u-boot-lpc.bin:	$(obj)u-boot.bin
+		./lpc17_fcg $(obj)u-boot.bin $(obj)u-boot-lpc.bin
+
+$(obj)u-boot-lpc.hex:	$(obj)u-boot-lpc.bin
+		$(OBJCOPY) ${OBJCFLAGS} -O ihex $< $@ -I binary
+
 $(obj)u-boot.srec:	$(obj)u-boot
 		$(OBJCOPY) -O srec $< $@
 
@@ -991,6 +1000,13 @@
 	@board/armltd/versatile/split_by_variant.sh $@
 
 #########################################################################
+# NXP development boards
+#########################################################################
+
+ea1788_config: unconfig
+	@$(MKCONFIG) ea1788 arm cortex-m3 ea1788 nxp lpc17xx
+
+#########################################################################
 ## XScale Systems
 #########################################################################
 
